Datasheet

311
3.15 JTAG Support
The PCI2050B bridge implements a JTAG test port based on IEEE Standard 1149.1, IEEE Standard Test Access Port
and Boundary-Scan Architecture. The JTAG test port consists of the following:
A 5-wire test access port
A test access port controller
An instruction register
A bypass register
A boundary-scan register
3.15.1 Test Port Instructions
The PCI2050B bridge supports the following JTAG instructions:
EXTEST, BYPASS, and SAMPLE
HIGHZ and CLAMP
Private (various private instructions used by TI for test purposes)
Table 34 lists and describes the different test port instructions, and gives the op code of each one. The information
in Table 35 is for implementation of boundary scan interface signals to permit in-circuit testing.
Table 34. JTAG Instructions and Op Codes
INSTRUCTION OP CODE DESCRIPTION
EXTEST 00000 External test: drives terminals from the boundary scan register
SAMPLE 00001 Sample I/O terminals
CLAMP 00100 Drives terminals from the boundary scan register and selects the bypass register for shifts
HIGHZ 00101 Puts all outputs and I/O terminals except for the TDO terminal in a high-impedance state
BYPASS 11111 Selects the bypass register for shifts
Table 35. Boundary Scan Terminal Order
BOUNDARY SCAN
REGISTER NUMBER
PDV/PPM TERMINAL
NUMBER
GHK/ZHK
TERMINAL NUMBER
TERMINAL
NAME
GROUP DISABLE
REGISTER
BOUNDARY-SCAN
CELL TYPE
0 137 J15 S_AD0 19 Bidirectional
1 138 H19 S_AD1 19 Bidirectional
2 140 H17 S_AD2 19 Bidirectional
3 141 H14 S_AD3 19 Bidirectional
4 143 G19 S_AD4 19 Bidirectional
5 144 G18 S_AD5 19 Bidirectional
6 146 G14 S_AD6 19 Bidirectional
7 147 F19 S_AD7 19 Bidirectional
8 149 G15 S_C/BE0 19 Bidirectional
9 150 F17 S_AD8 19 Bidirectional
10 152 F14 S_AD9 19 Bidirectional
11 153 E18 S_M66ENA 19 Bidirectional
12 154 F15 S_AD10 19 Bidirectional
13 155 E17 MS0 Input
14 158 E14 S_AD11 19 Bidirectional
15 161 B15 S_AD12 19 Bidirectional
16 162 A15 S_AD13 19 Bidirectional
17 164 B14 S_AD14 19 Bidirectional
18 165 E13 S_AD15 19 Bidirectional
19 Control