Datasheet

3−2
3.1.1 Write Combining
The PCI2050B bridge supports write combining for upstream and downstream transactions. This feature combines
separate sequential memory write transactions into a single burst transaction. This feature can only be used if the
address of the next memory write transaction is the next sequential address after the address of the last double word
of the previous memory transaction. For example, if the current memory transaction ends at address X and next
memory transaction starts at address X+1, then the PCI2050B bridge combines both transactions into a single
transaction.
The write combining feature of the PCI2050B bridge is enabled by default on power on reset. It can also be disabled
by setting bit 0 of the TI diagnostics register at offset F0h to 1.
3.1.2 66-MHz Operation
The PCI2050B bridge supports two 32-bit PCI buses operating at a maximum frequency of 66 MHz. The 66-MHz
clocking requires three terminals: P_M66ENA, S_M66ENA, and CONFIG66. To enable 66-MHz operation, the
CONFIG66 terminal must be tied high on the board. This sets the 66-MHz capable bit in the primary and secondary
status register. The P_M66ENA and S_M66ENA must not be pulled high unless CONFIG66 is also high.
The P_M66ENA and S_M66ENA signals indicate whether the primary or secondary interfaces are working at
66 MHz. This information is needed to control the frequency of the secondary bus. Note that PCI Local Bus
Specification (Revision 2.2) restricts clock frequency changes above 33 MHz during reset only.
The following frequency combinations are supported on the primary and secondary buses in the PCI2050B device:
• 66-MHz primary bus, 66-MHz secondary bus
• 66-MHz primary bus, 33-MHz secondary bus
• 33-MHz primary bus, 33-MHz secondary bus
The PCI2050B bridge does not support 33-MHz primary/66-MHz secondary bus operation. If CONFIG66 is high and
P_M66ENA is low, then the PCI2050B bridge pulls down S_M66ENA to indicate that secondary bus is running at
33 MHz.
The PCI2050B bridge generates the clock signals S_CLKOUT[9:0] for the secondary bus devices and its own
interface. It divides the P_CLK by 2 to generate the secondary clock outputs whenever the primary bus is running
at 66 MHz and secondary bus is running at 33 MHz. The bridge detects this condition by polling P_M66ENA and
S_M66ENA.
3.2 PCI Commands
The bridge responds to PCI bus cycles as a PCI target device based on internal register settings and on the decoding
of each address phase. Table 3−1 lists the valid PCI bus cycles and their encoding on the command/byte enable
(C/BE
) bus during the address phase of a bus cycle.