Datasheet

2−16
Table 2−12. Secondary PCI Interface Control Terminals
TERMINAL
NAME
PDV/
PPM
NO.
GHK/
ZHK
NO.
I/O DESCRIPTION
S_IRDY 177 C11 I/O
Secondary initiator ready. S_IRDY indicates the ability of the secondary bus master to complete the
current data phase of the transaction. A data phase is completed on a rising edge of S_CLK where both
S_IRDY
and S_TRDY are asserted; until S_IRDY and S_TRDY are asserted, wait states are inserted.
S_LOCK 172 C12 I/O
Secondary PCI bus lock. S_LOCK is used to lock the secondary bus and gain exclusive access as a
master.
S_PAR 168 C13 I/O
Secondary parity. In all secondary bus read and write cycles, the bridge calculates even parity across
the S_AD and S_C/BE
buses. As a master during PCI write cycles, the bridge outputs this parity indicator
with a one-S_CLK delay. As a target during PCI read cycles, the calculated parity is compared to the
master parity indicator. A miscompare can result in a parity error assertion (S_PERR).
S_PERR
171 E12 I/O
Secondary parity error indicator. S_PERR is driven by a secondary bus PCI device to indicate that
calculated parity does not match S_PAR when enabled through the command register (PCI offset 04h,
see Section 4.3).
S_REQ8
S_REQ7
S_REQ6
S_REQ5
S_REQ4
S_REQ3
S_REQ2
S_REQ1
S_REQ0
9
8
7
6
5
4
3
2
207
G5
F2
F3
E1
E2
G6
F5
E3
B4
I
Secondary PCI bus request signals. The bridge provides internal arbitration, and these signals are used
as inputs from secondary PCI bus masters requesting the bus. Ten potential masters (including the
bridge) can be located on the secondary PCI bus.
When the internal arbiter is disabled, the S_REQ0
signal is reconfigured as an external secondary bus
grant for the bridge.
S_SERR
169 B13 I
Secondary system error. S_SERR is passed through the primary interface by the bridge if enabled
through the bridge control register (PCI offset 3Eh, see Section 4.32). S_SERR
is never asserted by the
bridge.
S_STOP 173 B12 I/O
Secondary cycle stop signal. S_STOP is driven by a PCI target to request that the master stop the current
secondary bus transaction. S_STOP
is used for target disconnects and is commonly asserted by target
devices that do not support burst data transfers.
S_TRDY 176 B11 I/O
Secondary target ready. S_TRDY indicates the ability of the secondary bus target to complete the
current data phase of the transaction. A data phase is completed on a rising edge of S_CLK where both
S_IRDY and S_TRDY are asserted; until S_IRDY and S_TRDY are asserted, wait states are inserted.
Table 2−13. JTAG Interface Terminals
TERMINAL
NAME
PDV/
PPM
NO.
GHK/
ZHK
NO.
I/O DESCRIPTION
TCK 133 J19 I JTAG boundary-scan clock. TCK is the clock controlling the JTAG logic.
TDI 129 K18 I
JTAG serial data in. TDI is the serial input through which JTAG instructions and test data enter the JTAG
interface. The new data on TDI is sampled on the rising edge of TCK.
TDO 130 K17 O
JTAG serial data out. TDO is the serial output through which test instructions and data from the test logic
leave the PCI2050B device.
TMS 132 K14 I JTAG test mode select. TMS causes state transitions in the test access port controller.
TRST 134 J18 I
JTAG TAP reset. When TRST is asserted low, the TAP controller is asynchronously forced to enter a
reset state and initialize the test logic.