Datasheet

2−15
Table 2−11. Secondary PCI Address and Data Terminals
TERMINAL
NAME
PDV/
PPM
NO.
GHK/
ZHK
NO.
I/O DESCRIPTION
S_AD31
S_AD30
S_AD29
S_AD28
S_AD27
S_AD26
S_AD25
S_AD24
S_AD23
S_AD22
S_AD21
S_AD20
S_AD19
S_AD18
S_AD17
S_AD16
S_AD15
S_AD14
S_AD13
S_AD12
S_AD11
S_AD10
S_AD9
S_AD8
S_AD7
S_AD6
S_AD5
S_AD4
S_AD3
S_AD2
S_AD1
S_AD0
206
204
203
201
200
198
197
195
192
191
189
188
186
185
183
182
165
164
162
161
159
154
152
150
147
146
144
143
141
140
138
137
A4
E6
B5
A5
C6
B6
A6
C7
E8
F8
B8
A8
F9
C9
F10
E10
E13
B14
A15
B15
E14
F15
F14
F17
F19
G14
G18
G19
H14
H17
H19
J15
I/O
Secondary address/data bus. These signals make up the multiplexed PCI address and data bus on
the secondary interface. During the address phase of a secondary bus PCI cycle, S_AD31−S_AD0
contain a 32-bit address or other destination information. During the data phase, S_AD31−S_AD0
contain data.
S_C/BE3
S_C/BE2
S_C/BE1
S_C/BE0
194
180
167
149
B7
A10
F12
G15
I/O
Secondary bus commands and byte enables. These signals are multiplexed on the same PCI
terminals. During the address phase of a secondary bus PCI cycle, S_C/BE3
−S_C/BE0 define the bus
command. During the data phase, this 4-bit bus is used as byte enables. The byte enables determine
which byte paths of the full 32-bit data bus carry meaningful data. S_C/BE0 applies to byte 0
(S_AD7−S_AD0), S_C/BE1
applies to byte 1 (S_AD15−S_AD8), S_C/BE2 applies to byte 2
(S_AD23−S_AD16), and S_C/BE3
applies to byte 3 (S_AD31−S_AD24).
S_DEVSEL 175 A11 I/O
Secondary device select. The bridge asserts S_DEVSEL to claim a PCI cycle as the target device. As
a PCI master on the secondary bus, the bridge monitors S_DEVSEL
until a target responds. If no target
responds before time-out occurs, then the bridge terminates the cycle with a master abort.
S_FRAME 179 F11 I/O
Secondary cycle frame. S_FRAME is driven by the master of a secondary bus cycle. S_FRAME is
asserted to indicate that a bus transaction is beginning and data transfers continue while S_FRAME
is asserted. When S_FRAME is deasserted, the secondary bus transaction is in the final data phase.
S_GNT8
S_GNT7
S_GNT6
S_GNT5
S_GNT4
S_GNT3
S_GNT2
S_GNT1
S_GNT0
19
18
17
16
15
14
13
11
10
J1
H1
H2
H3
H5
G1
G2
H6
F1
O
Secondary bus grant to the bridge. The bridge provides internal arbitration and these signals are used
to grant potential secondary PCI bus masters access to the bus. Ten potential masters (including the
bridge) can be located on the secondary PCI bus.
When the internal arbiter is disabled, S_GNT0
is reconfigured as an external secondary bus request
signal for the bridge.