Datasheet

2−14

Table 2−10. Secondary PCI System Terminals

TERMINAL

NAME

PDV/

PPM

NO.

GHK/

ZHK

NO.

I/O DESCRIPTION

S_CLKOUT9

S_CLKOUT8

S_CLKOUT7

S_CLKOUT6

S_CLKOUT5

S_CLKOUT4

S_CLKOUT3

S_CLKOUT2

S_CLKOUT1

S_CLKOUT0

Secondary PCI bus clocks. Provide timing for all transactions on the secondary PCI bus. Each

secondary bus device samples all secondary PCI signals at the rising edge of its corresponding

S_CLKOUT input.

S_CLK

21 J3 I

Secondary PCI bus clock input. This input synchronizes the PCI2050B device to the secondary bus

clocks.

S_CFN 23 J6 I

Secondary external arbiter enable. When this signal is high, the secondary external arbiter is enabled.

When the external arbiter is enabled, the PCI2050B S_REQ0

terminal is reconfigured as a secondary

bus grant input to the bridge and S_GNT0

is reconfigured as a secondary bus master request to the

external arbiter on the secondary bus.

S_RST 22 J5 O

Secondary PCI reset. S_RST is a logical OR of P_RST and the state of the secondary bus reset bit

(bit 6) of the bridge control register (PCI offset 3Eh, see Section 4.32). S_RST

is asynchronous with

respect to the state of the secondary interface CLK signal.