Datasheet
2−12
The terminals are grouped in tables by functionality, such as PCI system function and power-supply function (see
Table 2−7 through Table 2−15). The terminal numbers also are listed for convenient reference.
Table 2−7. Primary PCI System Terminals
TERMINAL
NAME
PDV/
PPM
NO.
GHK/
ZHK
NO.
I/O DESCRIPTION
P_CLK 45 P3 I
Primary PCI bus clock. P_CLK provides timing for all transactions on the primary PCI bus. All primary PCI
signals are sampled at rising edge of P_CLK.
P_RST
43 P2 I
PCI reset. When the primary PCI bus reset is asserted, P_RST causes the bridge to put all output buffers
in a high-impedance state and reset all internal registers. When asserted, the device is completely
nonfunctional. During P_RST
, the secondary interface is driven low. After P_RST is deasserted, the bridge
is in its default state.
Table 2−8. Primary PCI Address and Data Terminals
TERMINAL
NAME
PDV/
PPM
NO.
GHK/
ZHK
NO.
I/O DESCRIPTION
P_AD31
P_AD30
P_AD29
P_AD28
P_AD27
P_AD26
P_AD25
P_AD24
P_AD23
P_AD22
P_AD21
P_AD20
P_AD19
P_AD18
P_AD17
P_AD16
P_AD15
P_AD14
P_AD13
P_AD12
P_AD11
P_AD10
P_AD9
P_AD8
P_AD7
P_AD6
P_AD5
P_AD4
P_AD3
P_AD2
P_AD1
P_AD0
49
50
55
57
58
60
61
63
67
68
70
71
73
74
76
77
93
95
96
98
99
101
107
109
112
113
115
116
118
119
121
122
R3
T1
R6
W5
U6
R7
W6
U7
U8
V8
W9
V9
R9
P9
V10
U10
W14
R13
U14
P14
V15
U15
R17
N14
P17
P18
P19
M14
N18
N19
M17
M18
I/O
Primary address/data bus. These signals make up the multiplexed PCI address and data bus on the
primary interface. During the address phase of a primary bus PCI cycle, P_AD31−P_AD0 contain a
32-bit address or other destination information. During the data phase, P_AD31−P_AD0 contain data.
P_C/BE3
P_C/BE2
P_C/BE1
P_C/BE0
64
79
92
110
V7
P10
P13
R18
I/O
Primary bus commands and byte enables. These signals are multiplexed on the same PCI terminals.
During the address phase of a primary bus PCI cycle, P_C/BE3
−P_C/BE0 define the bus command.
During the data phase, this 4-bit bus is used as byte enables. The byte enables determine which byte
paths of the full 32-bit data bus carry meaningful data. P_C/BE0 applies to byte 0 (P_AD7−P_AD0),
P_C/BE1
applies to byte 1 (P_AD15−P_AD8), P_C/BE2 applies to byte 2 (P_AD23−P_AD16), and
P_C/BE3
applies to byte 3 (P_AD31−P_AD24).