Datasheet

7−3
7.3 Electrical Characteristics Over Recommended Operating Conditions (unless
otherwise noted)
PARAMETER PINS OPERATION TEST CONDITIONS MIN MAX UNIT
PCI
3.3 V
I
OH
= −0.5 mA 0.9 V
CC
V
OH
High-level output voltage
†
PCI
5 V
I
OH
= −2 mA 2.4
V
V
OH
High-level output voltage
†
HPI
‡
I
OH
= −8 mA V
CC
−0.6
V
Miscellaneous
§
I
OH
= −4 mA
V
CC
−0.6
Miscellaneous
§
I
OH
= −4 mA V
CC
−0.
6
PCI
3.3 V
I
OL
= 1.5 mA 0.1 V
CC
PCI
5 V
I
OL
= 6 mA 0.55
V
OL
Low-level output voltage
HPI
‡
I
OL
= 8 mA 0.5
V
OL
Miscellaneous
§
/
Failsafe¶
I
OL
= 4 mA 0.5
3-state output, high-impedance
PCI/HPI
3.6 V
V
I
= V
CC
10
V
I
OZH
3-state output, high-impedance
state current
PCI/HPI
5.5 V
V
I
= V
CC
20
V
I
OZH
state current
Failsafe 3.6 V V
I
= V
CC
10 µA
I
OZL
3-state output, high-impedance
state current
Output only pins V
I
= GND −10 µA
I
IH
#
High-level input current
Input only and I/O pins
3.6 V
V
I
= V
CC
10
µA
I
IH
#
High-level input current
Input only and I/O pins
5.5 V V
I
= V
CC
20
µ
A
I
IL
#
Low-level input current
Input only pins V
I
= GND −1
A
I
IL
#
Low-level input current
I/O pins V
I
= GND −10
µA
†
V
OH
is not tested on PCI_SERR
, PCI_INTA, PME, and HSENUM due to open-drain configuration.
‡
HPI pins are all other TTL/LVCMOS pins.
§
TTL/LVCMOS pins are GP_RST
, HCS3−HCS0, and HRST3−HRST0.
¶
Failsafe pins are PME
and HSENUM.
#
For I/O pins, input leakage (I
IL
and I
IH
) includes I
OZ
leakage of the disabled output.