Datasheet

6−9
6.3.2 Address/Data Bus
The HPI provides 32-bit data to the CPU with a 16-bit wide parallel external interface (C54x has 8-bit wide external
interface). All transfers with the host consist of two consecutive half-words. On the HPI data register data write access,
HBE1
and HBE0 (byte enables) select the bytes in 32-bit word to be written. For the HPI address register, HPI control
register, and HPI data register read, byte enables are not used. The HWIL pin determines whether the first or second
byte is being transferred and HWOB bit in the HPI control register (see Section 6.3.5) determines whether the first
half-word is most significant or least significant. The host must not break the first half-word/second half-word
sequence or data may be lost, in the case of full word access.
6.3.3 Byte Enables (HBE0 and HBE1)
On the HPI data register writes, the value of HBE0 and HBE1 indicate which bytes of the 32-bit word are written. The
value of byte enables, as mentioned earlier, is not important on HPI address or HPI control register accesses and
HPI data register reads. On HPI data register writes, the HBE0
enables the least significant byte in the half-word while
HBE1
determines the most significant byte in the half-word. Following combinations for the HBE0/HBE1 are allowed:
• For byte writes, one HBEn
in either of the half-word accesses can be enabled.
• For half-word writes, both HBE0
and HBE1 must be active low in either half-word access (but not both
half-words).
• For complete word writes, both HBE0
and HBE1 must be held active low in both half-word accesses
• No other combinations are valid.
6.3.4 Wait States
In C6x based systems, wait states can be inserted either using HRDY signal as in the case of C54X, or using the
HRDY bit in the HPI control register (see Section 6.3.5).