Datasheet

6−7
PCI_CLK
HRST2
HCS2
HAD[15:0]
HCNTL0
HCNTL1
HWIL
HDS
HR/W
HRDY5X2
ZZZZ ZZAA ZZBB
12 3 4 567 8 9
Figure 6−3. Word Write From HPID Without Auto-Increment Enabled
6.2.7.3 PCI Double Word Write
In the third example depicted in Figure 6−4, a PCI write transaction with address FFEF3800, byte enables of 0000b,
and a single data phase occurs of the PCI bus. The data is DDCCBBAAh. The PCI2040 takes this PCI transaction
and translates it to an 8-bit host port transaction. This example is a little different than a normal write due to the fact
that this PCI transaction is specifying a write to HPID without auto-increment selected. Typically, when performing
a doubleword read or write to the HPID, the PCI address should specify HPID with auto-increment selected. Because
auto-increment was not selected, the PCI2040 attempts to place the data in two different locations in the DSP’s
memory. The event flow is as follows:
1. The host port is idle.
2. HCNTL0 and HCNTL1 are driven high indicating to the C5410 that this transaction is going to target the
HPID without auto-increment enabled. The HR/W
is driven low indicating to the C5410 that this transaction
is a write.
3. HCS1
is asserted indicating that this transaction is targeting DSP1. The first byte or half-word is driven onto
the HAD bus. Also during clock 3 the HDS
is asserted. During this time, the C5410 latches the values of
HCNTL1, HCNTL0, HWIL, and HR/W
.
4. The PCI2040 samples the state of HRDY5X0. If the C5410 indicates it is not ready, then the PCI2040 waits
until the C5410 indicates it is ready before it deasserts HDS
and HWIL.
5. Because the state of the HRDY5X0 signal indicates the C5410 is ready, the PCI2040 deasserts HDS
. The
C5410 latches the data, AAh, on the rising edge of HDS
. The HWIL is driven high.
6. Same as Step 3.
7. Same as Step 4 except the HCNTL1 is driven low. Because a write to the HPID with auto-increment select
will pre-increment the HPIA, the HCNTL1 is driven low to increment the HPIA. This places the most
significant word of the PCI data to a different location in the DSP’s memory than the least significant word
was placed.
8. Same as Step 5 except the data latched by the C5410 is BBh.
9. Same as Step 3.
10. Same as Step 4.
11. Same as Step 5 except the data latched by the C5410 is CCh.