Datasheet

6−6
PCI_CLK
HRST0
HCS0
HAD[15:0]
HCNTL0
HCNTL1
HWIL
HDS
HR/W
HRDY5X0
XXAA XXBB
12345678
Figure 6−2. Word Write To HPID Without Auto-Increment Enabled
6.2.7.2 PCI Word Read
The second example outlined in Figure 6−3 shows how the PCI2040 translates a word read on the PCI bus with a
PCI address of FFEF5800h. The event flow is as follows:
1. The host port is idle.
2. HCNTL0 and HCNTL1 are driven high indicating to the C5410 that this transaction is going to target the
HPID without auto-increment enabled. The HR/W
is driven high indicating to the C5410 that this transaction
is a read.
3. HCS2
is asserted indicating that this transaction is targeting DSP0. The first byte or half-word is driven onto
the HAD bus. Also during clock 3 the HDS
is asserted. During this time, the C5410 latches the values of
HCNTL1, HCNTL0, HWIL, and HR/W
.
4. The PCI2040 samples the state of HRDY5X0. If the C5410 indicates it is not ready, then the PCI2040 waits
until the C5410 indicates it is ready before it deasserts HDS
and HWIL. In this case, the C5410 is not ready.
5. Same as Step 4 but in this case the C5410 is ready.
6. The PCI2040 drives both HDS
and HWIL high. The PCI2040 also latches the data on the lower eight data
lines (HAD7−HAD0).
7. Same as Step 3.
8. Same as Step 5.
9. Same as Step 6 except the data latched is BBh and HCS2
is deasserted indicating the end of the
transaction. The PCI2040 then places XXXXBBAAh on the PCI bus.