Datasheet

6−4
A C54x interrupt is generated when the host writes a 1 to the DSPINT bit (bit 2) of the HPI control register. This
interrupt can be used to wake up DSP from IDLE. The host and C54x always read this bit as 0. Once a 1 is written
to DSPINT by the host, a 0 need not be written before generating another interrupt. A DSP write or writing a 0 to this
bit has no effect.
The host should not write a 1 to the DSPINT bit while writing to BOB or HINT and the DSP should not write a 1 to the
HINT bit while writing to SMOD bit or an unwanted interrupt will be generated.
6.2.3 Four Strobes (HDS1, HDS2, HR/W, HAS)
HPI has four strobes and they are:
• Two data strobes (HDS1
and HDS2)
• Read/write strobe (HR/W
)
• Address strobe (HAS
)
The HCS
input serves primarily as the enable input for the HPI and HDS1 and HDS2 control the HPI data transfer.
The equivalent circuit of these three inputs is shown in the figure below. This figure shows that the internal strobe
signal that samples the HCNTL1, HCNTL0, HWIL, and HR/W
(when HAS is not used) is derived from all three input
signals. So the latest of the HCS
, HDS1, and HDS2 control the sampling of these inputs.
HCS
HDS2
HDS1
Internal Strobe
Figure 6−1. C54X Select Input Logic
6.2.4 Wait States
The HPI ready pin (HRDY) allows insertion of wait states to allow deferred completion of access cycles for hosts that
have faster cycle times that the HPI can accept due to C54x operating clock rates. The PCI2040 has four HRDY
signals, one for each DSP. The HRDY signal will automatically adjust the host access rate to a faster DSP clock rate
or switch the HPI mode (to HOM) for faster access.
6.2.5 Host Read/Write Access to HPI
The host begins accessing the HPI interface first by initializing the HPI control register, then by initializing the HPI
address register, and then by reading data from or writing data to the HPI data register. Writing to the HPI address
or HPI data register initiates an internal cycle that transfers the desired data between the HPI data register and the
internal HPI memory. This process may take several cycles. Each time an access is made, data written to HPI data
register is not written to HPI memory until after the host access cycle and the data read from HPI data register is the
data from the previous cycle. Therefore, when reading, the data is obtained from the location specified in the previous
access and the current access serves as an initiation of the next cycle. A similar operation occurs for the write
operation. The data written to the HPI data register is not written to HPI memory until after the external cycle is
completed. If the HPI data register read operation immediately follows an HPI data register write operation, then the
same data (the data written) is read.
During random transfers or sequential transfers selected with auto-increment with a significant amount of time
between them, the HPI address register must be either rewritten, or two reads from the same location must be done,
or an address write prior to read must be made to ensure that the most recent data is read because the DSP may
have changed the contents of the location being accessed.
In SAM, the HRDY signal is used to insert wait states if necessary. However, this signal is inactive in HOM. Unless
back-to-back transfers are being performed, HRDY signal is normally high when the first byte of the cycle is
transferred. HRDY is always high when HCS
is high and it is not used and stays high in SAM when reading the HPI
control or HPI address register or writing to the HPI control register (except writing a 1 to either DSPINT or HINT).