Datasheet

5−5
5.5 HPI DSP Implementation Register
The HPI DSP implementation register is used to indicate the presence of implemented DSPs on the HPI interface
and is loaded from the serial ROM.
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name HPI DSP implementation
Type R R R R R R R R R R R R RWU RWU RWU RWU
Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Register: HPI DSP implementation
Type: Read/Write/Update
Offset: 16h
Default: 0000h
Table 5−6. HPI DSP Implementation Register
BIT FIELD NAME TYPE DESCRIPTION
15−4 RSVD R Reserved. Bits 15−4 return 0s when read.
3 DSP_PRSNT3 RWU DSP3 present. Bit 3 indicates if the DSP3 is present on the HPI interface.
2 DSP_PRSNT2 RWU DSP2 present. Bit 2 indicates if the DSP2 is present on the HPI interface.
1 DSP_PRSNT1 RWU DSP1 present. Bit 1 indicates if the DSP1 is present on the HPI interface.
0 DSP_PRSNT0 RWU DSP0 present. Bit 0 indicates if the DSP0 is present on the HPI interface.
5.6 HPI Data Width Register
The HPI data width register is used to determine if the implemented DSPs are C54x or C6x, and is loaded from the
serial ROM. Each bit in this register is meaningful only if the corresponding bit in the HPI DSP implementation register
is set (see Section 5.5).
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name HPI data width
Type R R R R R R R R R R R R RWU RWU RWU RWU
Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Register: HPI data width
Type: Read/Write/Update
Offset: 18h
Default: 0000h
Table 5−7. HPI Data Width Register
BIT FIELD NAME TYPE DESCRIPTION
15−4 RSVD R Reserved. Bits 15−4 return 0s when read.
3 DWIDTH3 RWU When bit 3 is set, the HPI[3] data bus is 16 bits (C6x). When bit 3 is 0, it is 8 bits (C54x).
2 DWIDTH2 RWU When bit 2 is set, the HPI[2] data bus is 16 bits (C6x). When bit 2 is 0, it is 8 bits (C54x).
1 DWIDTH1 RWU When bit 1 is set, the HPI[1] data bus is 16 bits (C6x). When bit 1 is 0, it is 8 bits (C54x).
0 DWIDTH0 RWU When bit 0 is set, the HPI[0] data bus is 16 bits (C6x). When bit 0 is 0, it is 8 bits (C54x).