Datasheet

5−4

5.3 HPI Error Report Register

The HPI error report register reflects the state of errors on the HPI interfaces. If any bits in this register are set, then

the PCI2040 sets bit 30 (HPIError) in the interrupt event register (see Section 5.1). Software can set the bits in this

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Name HPI error report

Type R R R R R R R R R R R R RWU RWU RWU RWU

Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Type: Read/Write/Update

Offset: 10h

Default: 0000h

Table 5−4. HPI Error Report Register

BIT FIELD NAME TYPE DESCRIPTION

15−4 RSVD R Reserved. Bits 15−4 return 0s when read.

3−0 HPIErr[3:0] RWU

PCI2040 sets this bit if a serious error occurs on the HPI[x] interface. The error conditions that cause this

bit to be set are as follows:

1. HRDY5xn (or HRDY6xn) driven by DSPn not sampled asserted within 256 PCI clocks following

the assertion of HCSn

by PCI2040

2. When the discard timeout expires for a read transaction from HPI[x]

3. A PCI byte enable combination other than 4’b1100, 4’b0011, or 4’b0000 was received for a

transaction destined for a C54x DSP on HPI[x]

5.4 HPI Reset Register

The HPI reset register is used to cause resets to the DSP interfaces. The implemented bits in this register are in the

PME context for PCI2040 and default to set. Thus, a GRST

causes all DSP interfaces to be reset, and software is

responsible for removing the HRSTn

to the DSP interfaces.

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Name HPI reset

Type R R R R R R R R R R R R RW RW RW RW

Default 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1

Type: Read-only, Read/Write

Offset: 14h

Default: 000Fh

Table 5−5. HPI Reset Register

BIT FIELD NAME TYPE DESCRIPTION

15−4 RSVD R Reserved. Bits 15−4 return 0s when read.

3 HPI3_RST RW HPI reset 3. When bit 3 is set, HRST3 is asserted.

2 HPI2_RST RW HPI reset 2. When bit 2 is set, HRST2 is asserted.

1 HPI1_RST RW HPI reset 1. When bit 1 is set, HRST1 is asserted.

0 HPI0_RST RW HPI reset 0. When bit 0 is set, HRST0 is asserted.