Datasheet

5−3
5.2 Interrupt Mask Register
The interrupt mask register is used to enable the various PCI2040 interrupt sources. Reads from either the set register
or the clear register always return interrupt mask. In all cases, except masterIntEnable (bit 31), the enables for each
interrupt event align with the event register bits detailed in Table 5−2.
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name Interrupt mask
Type RSC RSC RSC RSC RSC RSC R R R R R R R R R R
Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name Interrupt mask
Type R R R R R R R R R R R R RSC RSC RSC RSC
Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Register: Interrupt mask
Type: Read/Set/Clear
Offset: 08h Set Register
0Ch Clear Register
Default: 0000 0000h
Table 5−3. Interrupt Mask Register
BIT FIELD NAME TYPE DESCRIPTION
31 masterIntEnable RSC
When bit 31 is set, external interrupts are generated in accordance with this register. If bit 31 is 0, then
no external interrupts are generated.
30 HPIError RSC
When bit 30 is set and the interrupt event register, HPIError bit (see Table 5−2, bit 30) is also set, an
interrupt is generated. When set, the HPI state machine will never cause target aborts on PCI and will
return the PCI slave 0s on such errors.
When set, errors on posted writes will not cause SERR
signal assertions enabled by bit 8 (SERR_EN)
in the PCI command register (see Section 4.3). When bit 30 is 0, target aborts may occur and SERR
may be signaled as a result of a posted write error.
29 GPError RSC
When bit 29 is set and the interrupt event register, GPError bit (see Table 5−2, bit 29) is also set, an
interrupt is generated. When set, the GP state machine will never cause target aborts on PCI and will
return the PCI slave 0s on such errors. When bits 29 and 30 are set, errors on posted writes will not cause
SERR
signal assertions enabled by bit 8 (SERR_EN) in the PCI command register (see Section 4.3).
Both bits 29 and 30 need to be set to prevent target aborts.
28 IntGPIO3 RSC
When bit 28 is set and the corresponding interrupt event register bit (see Table 5−2, bit 28) is also set,
an interrupt is generated. When bit 28 is 0, the interrupt is masked.
27 IntGPIO2 RSC
When bit 27 is set and the corresponding interrupt event register bit (see Table 5−2, bit 27) is also set,
an interrupt is generated. When bit 27 is 0, the interrupt is masked.
26 GPINT RSC
When bit 26 is set and the corresponding interrupt event register bit (see Table 5−2, bit 26) is also set,
an interrupt is generated. When bit 26 is 0, the interrupt is masked.
25−4 RSVD R Reserved. Bits 25−4 return 0s when read.
3 IntDSP3 RSC
When bit 3 is set and the corresponding interrupt event register bit (see Table 5−2, bit 3) is also set, an
interrupt is generated. When bit 3 is 0, the interrupt is masked.
2 IntDSP2 RSC
When bit 2 is set and the corresponding interrupt event register bit (see Table 5−2, bit 2) is also set, an
interrupt is generated. When bit 2 is 0, the interrupt is masked.
1 IntDSP1 RSC
When bit 1 is set and the corresponding interrupt event register bit (see Table 5−2, bit 1) is also set, an
interrupt is generated. When bit 1 is 0, the interrupt is masked.
0 IntDSP0 RSC
When bit 0 is set and the corresponding interrupt event register bit (see Table 5−2, bit 0) is also set, an
interrupt is generated. When bit 0 is 0, the interrupt is masked.