Datasheet

5−2
5.1 Interrupt Event Register
The interrupt event register reflects the state of the various PCI2040 interrupt sources. The interrupt bits are set by
an asserting edge of the corresponding interrupt signal or by writing a 1 in the corresponding bit in the set register.
The only mechanism to clear the bits in this register is to write a 1 to the corresponding bit in the clear register. Note
that the interrupt event register itself is returned on reads from the interrupt event set register (offset 00h), but the
bit-wise AND of the interrupt event and interrupt mask registers is returned on reads from the interrupt event clear
register (offset 04h).
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name Interrupt event
Type R RU RSCU RSCU RSCU RSCU R R R R R R R R R R
Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name Interrupt event
Type R R R R R R R R R R R R RSCU RSCU RSCU RSCU
Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Register: Interrupt event
Type: Read/Set/Clear/Update
Offset: 00h Set Register
04h Clear Register [Returns IntEvent & IntMask when read]
Default: 0000 0000h
Table 5−2. Interrupt Event Register
BIT FIELD NAME TYPE DESCRIPTION
31 RSVD R Reserved. Bit 31 returns 0 when read.
30 HPIError RU
Bit 30 is set upon serious error conditions on the HPI interface, and allows software to gracefully terminate
communication with an HPI device. This bit is the OR combination of the HPI errors in the HPI error report
register (see Section 5.3).
29 GPError RSCU
Bit 29 is set upon serious error conditions on the GP interface, and allows software to gracefully terminate
communication with a GP device.
28 IntGPIO3 RSCU
Set when GPIO3Pin (see Section 4.21, bit 3) selects GPIO3 as an interrupt event input, and the event type
selected by the GPIO interrupt event type register occurs (see Section 4.25).
27 IntGPIO2 RSCU
Set when GPIO2Pin (see Section 4.21, bit 2) selects GPIO2 as an interrupt event input, and the event type
selected by the GPIO interrupt event type register occurs (see Section 4.25).
26 GPINT RSCU
The PCI2040 sets this bit if an interrupt has been generated by a device connected to the GPINT interface.
Software can set this bit for diagnostics.
25−4 RSVD R Reserved. Bits 25−4 return 0s when read.
3 IntDSP3 RSCU
The PCI2040 sets this bit if an interrupt has been generated by a device connected to the HPI[3] interface.
Software can set this bit for diagnostics.
2 IntDSP2 RSCU
The PCI2040 sets this bit if an interrupt has been generated by a device connected to the HPI[2] interface.
Software can set this bit for diagnostics.
1 IntDSP1 RSCU
The PCI2040 sets this bit if an interrupt has been generated by a device connected to the HPI[1] interface.
Software can set this bit for diagnostics.
0 IntDSP0 RSCU
The PCI2040 sets this bit if an interrupt has been generated by a device connected to the HPI[0] interface.
Software can set this bit for diagnostics.