Datasheet

4−20
4.34 HS Next-Item Pointer Register
The HS next-item pointer register is used to indicate the next item in the linked list of the PCI extended capabilities.
This register returns 00h indicating no additional capabilities are supported.
Bit 7 6 5 4 3 2 1 0
Name HS next-item pointer
Type R R R R R R R R
Default 0 0 0 0 0 0 0 0
Register: HS next-item pointer
Type: Read-only
Offset: 5Dh
Default: 00h
4.35 CPCI Hot Swap Control and Status Register
The CPCI hot swap control and status register (HS_CSR) provides the control and status information about the
compact PCI hot swap resources.
Bit 7 6 5 4 3 2 1 0
Name CPCI hot swap control and status
Type RCU RCU R R RW R RW R
Default 0 0 0 0 0 0 0 0
Register: CPCI hot swap control and status
Type: Read/Clear/Update/Write
Offset: 5Eh
Default: 00h
Table 4−18. CPCI Hot Swap Control and Status Register
BIT FIELD NAME TYPE DESCRIPTION
7 INS RCU
ENUM insertion status. When set, the HSENUM output is driven by the PCI2040. This bit defaults to 0, and
will be set after a PCI_RST
occurs, the preload of serial ROM is complete (miscellaneous control register,
bit 13 [SEEBS] is 0), the ejector handle is closed (miscellaneous control register, bit 8 [HSSWITCH_STS] is
0), and bit 6 (EXT) is 0. Thus, this bit is set following an insertion when the board implementing the PCI2040
is ready for configuration. This bit cannot be set under software control.
6 EXT RCU
ENUM extraction status. When set, the HSENUM output is driven by the PCI2040. This bit defaults to 0, and
is set when the ejector handle is opened (miscellaneous control register, bit 8 [HSSWITCH_STS] is 1) and bit 7
(INS) is 0. Thus, this bit is set when the board implementing the PCI2040 is about to be removed. This bit cannot
be set under software control.
5−4 RSVD R Reserved. Bits 5 and 4 return 0s when read.
3 LOO RW
LED on/off. This bit defaults to 0, and controls the external LED indicator (HSLED) under normal conditions.
However, for a duration following a PCI_RST
, the HSLED output is driven high by the PCI2040 control and this
bit will be ignored. When this bit is interpreted, a 1 will cause HSLED high and a 0 will cause HSLED low.
Following PCI_RST
, the HSLED output is driven high by the PCI2040 until both the pre-load of serial ROM
(miscellaneous control register, bit 13 [SEEBS] is 0), and the ejector handle is closed (miscellaneous control
register, bit 8 [HSSWITCH_STS] is 0). When these conditions are met, the HSLED is under software control
via bit 3 (LOO).
2 RSVD R Reserved. Bit 2 returns 0 when read.
1 EIM RW
ENUM interrupt mask. This bit allows the HSENUM output to be masked by software. Bits 7 (INS) and 6 (EXT)
are set independently from bit 1.
0 = Enable HSENUM output
1 = Mask HSENUM
output
0 RSVD R Reserved. Bit 0 returns 0 when read.