Datasheet

4−18
4.31 Power Management Control/Status Register
The power management control/status register determines and changes the current power state of the PCI2040. The
contents of this register are not affected by the internally generated reset caused by the transition from the D3
hot
to
D0 state. All PCI registers will be reset as a result of a D3
hot
-to-D0 state transition. TI specific registers, PCI power
management registers, and the legacy base address register are not reset.
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name Power management control/status
Type RCU R R R R R R RW R R R R R R RW RW
Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Register: Power management control/status
Type: Read/Clear/Update/Write
Offset: 54h
Default: 0000h
Table 4−16. Power Management Control/Status Register
BIT FIELD NAME TYPE DESCRIPTION
15 PME_STS RCU
PME status. This bit is set when the PME signal is asserted, independent of the state of bit 8 (PME_EN).
This bit is cleared by a write back of 1, and this also clears the PME
signal if PME was asserted. Writing
a 0 to this bit has no effect. This bit will NOT be cleared by the assertion of PCI_RST
. It will only be cleared
by the assertion of GRST
.
14−13 DATASCALE R Data scale. This two-bit field returns 0s when read.
12−9 DATASEL R Data select. This four-bit field returns 0s when read.
8 PME_EN RW
PME enable. This bit enables the function to assert PME. If bit 8 is cleared, then assertion of PME is
disabled. Bit 8 is NOT cleared by the assertion of PCI_RST
. It is only cleared by the assertion of GRST.
7−2 RSVD R Reserved. Bits 7−2 return 0s when read.
1−0 PWRSTATE RW
Power state. This two-bit field is used both to determine the current power state of a function, and to set
the function into a new power state. This field is encoded as:
00 = D0
01 = D1
10 = D2
11 = D3
hot