Datasheet

4−17
4.29 PM Next-Item Pointer Register
The PM next-item pointer register provides a pointer into the PCI configuration header where the CPCI hot swap
control and status register (HS_CSR) resides. The PCI header at 5Ch provides the hot swap register. If bit 3 (HSEN)
in the miscellaneous control register (see Section 4.26) is 0, then the PM next-item pointer register returns 00h when
read indicating the end of the extended capability list.
Bit 7 6 5 4 3 2 1 0
Name PM next-item pointer
Type R R R R R R R R
Default 0 1 0 1 1 1 0 0
Register: PM next-item pointer
Type: Read-only
Offset: 51h
Default: 5Ch
4.30 Power Management Capabilities Register
The power management capabilities (PMC) register contains information on the capabilities of the PCI2040 related
to power management. The PCI2040 supports all D0−D3 power states.
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name Power management capabilities
Type R R R R R R R R R R R R R R R R
Default 1 1 1 1 1 1 1 0 0 0 0 1 0 0 0 1
Register: Power management capabilities
Type: Read-only
Offset: 52h
Default: FE11h
Table 4−15. Power Management Capabilities Register
BIT FIELD NAME TYPE DESCRIPTION
15 D3cold_PMESupport R(W)
D3
cold
PME support. This bit defaults to read-only and becomes read/write when bit 2
(D3COLD_LOCK) in the miscellaneous control register is set (see Section 4.26). This bit defaults
to 1 indicating the PME signal can be asserted from the D3
cold
state. This bit is read/write
because wake-up support from D3
cold
is contingent on the system providing an auxiliary power
source to the Vcc terminals. If auxiliary power is not provided to Vcc terminals for D3
cold
wake-up,
then this bit should be cleared. This bit is not reset by the assertion of PCI_RST
, but is reset by
GRST
.
14−11 PME Support R
This field has a value of 4’b1111 indicating that the PCI2040 can signal PME from the D3
hot
, D2,
D1 and D0 states.
10 D2_Support R This bit returns a 1 when read indicating that the PCI2040 supports D2.
9 D1_Support R This bit returns a 1 when read indicating that the PCI2040 supports D1.
8−6 RSVD R Reserved. Bits 8−6 return 0s when read.
5 DSI R
Device specific initialization. This bit returns 0 when read indicating no special initialization is
required before a standard driver can use the PCI2040.
4 AUX_PWR R
Auxiliary power source. Bit 4 returns 1 when read indicating PME support in D3
cold
requires an
auxiliary power source.
3 PMECLK R
This bit returns 0 when read indicating that no PCI clock is required for the function to generate
PME
.
2−0 Version R
These three bits return 001b when read indicating compliance to PCI Bus Power Management
Interface Specification.