Datasheet

4−16

4.27 Diagnostic Register

The diagnostic register is provided for test purposes and should not be accessed during normal operation.

Bit 7 6 5 4 3 2 1 0

Name Diagnostic

Type RW R R RW RW R RW RW

Default 0 0 0 0 0 0 0 0

Type: Read/Write

Offset: 4Fh

Default: 00h

Table 4−14. Diagnostic Register

BIT FIELD NAME TYPE DESCRIPTION

7 TRUE_VAL RW True value. When set, all 1s are returned in the PCI vendor and device ID registers.

6−5 RSVD R Reserved. Bits 6−5 return 0s when read.

4 DIAG4 RW

Diagnostic RETRY_DIS. Delayed transaction disable. When bit 4 is set, delayed transactions are

disabled. When bit 4 is 0 (default), they are enabled.

3 DIAG3 RW

Diagnostic RETRY_EXT. When set, the PCI2040 extends the target latency from 16 to 64 PCI clocks and

is not PCI Local Bus Specification, Revision 2.2 compliant.

2 RSVD R Reserved. Bit 2 returns 0 when read.

1 ErrorTimer RW

Error timer. Bit 1 is used to enable/disable the error timer. By default, the timer is enabled but can be

disabled by writing a 1 to this bit.

0 TI_TEST RW

TI_TEST_BIT. This is internal TI test bit used by the design.

0 = Disable state vectors to GPIOs (default)

1 = Enable state vectors to GPIOs

4.28 PM Capability ID Register

The PM capability ID register identifies the linked list item as the register for PCI power management. This register

returns 01h when read, which is the unique ID located by the PCI SIG for the PCI location of the capabilities pointer

and the value.

Bit 7 6 5 4 3 2 1 0

Name PM capability ID

Type R R R R R R R R

Default 0 0 0 0 0 0 0 1

Type: Read-only

Offset: 50h

Default: 01h