Datasheet

4−15
4.26 Miscellaneous Control Register
The miscellaneous control register controls various miscellaneous functions.
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name Miscellaneous control
Type RU RCU R R R R R R R R RW RW RW RW RW RW
Default 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1
Register: Miscellaneous control
Type: Read/Clear/Update/Write
Offset: 4Ch
Default: 000Fh
Table 4−13. Miscellaneous Control Register
BIT FIELD NAME TYPE DESCRIPTION
15 SEEDS RU
Serial EEPROM detect status. When this bit is set, it indicates that serial EEPROM block has detected
an EEPROM.
14 SEEBES RCU
Serial EEPROM error status. When set, an error has occurred on the serial ROM interface. Writing a
1 to this bit clears the error status.
13 SEEBS R Serial EEPROM busy status. When set, the serial ROM interface is busy.
12−9 RSVD R Reserved. Bits 12−9 return 0s when read.
8 HSSWITCH_STS R
Hot swap switch status. Returns logical value of HSSWITCH input.
0 = Handle closed
1 = Handle open
7−6 RSVD R Reserved. Bits 7−6 return 0s when read.
5 GP_EN R
GP bus enable.
0 = GP bus disabled. (default)
1 = GP bus enabled.
4 PM11_EN R
PCI PM Specification 1.1 enable.
0 = Use PCI PM 1.0 register implementation (Default)
1 = Use PCI PM 1.1 register implementation
3 HSEN R
Hot swap enable.
0 = Hot swap disabled
1 = Hot swap enabled (default)
2 D3COLD_LOCK R
Lock bit for PME support from D3
cold
.
0 = Bit 15 (D3cold_PMESupport) in the power management capabilities register is read/write
(see Section 4.30)
1 = Bit 15 (D3cold_PMESupport) in the power management capabilities register is read-only
(default) (see Section 4.30)
1 PWDIS R
Posted write disable bit.
0 = Posted writes are disabled
1 = Posted writes are enabled (default)
0 SUBSYSRW R
Subsystem read write enable.
0 = Subsystem ID and subsystem vendor ID registers are read/write
1 = Subsystem ID and subsystem vendor ID registers are read-only (default)