Datasheet

4−9
4.13 GP Bus Base Address Register
The GP bus base address register is used by the PCI2040 to communicate with a device on the GP bus. This 32−bit
register allows software to assign a memory window for the GP bus anywhere in the 4-Gbyte address space. This
window has a 256-byte granularity which means the lower 8 bits of this register default to 0 and are read-only. This
register is controlled via bit 5 (GP_EN) in the miscellaneous control register (see Section 4.26) and if it is set to 0,
then this register will be read-only and always return 0000 0000h when read.
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name GP bus base address
Type RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW
Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name GP bus base address
Type RW RW RW RW RW RW RW RW R R R R R R R R
Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Register: GP bus base address
Type: Read-only, Read/Write
Offset: 18h
Default: 0000 0000h
Table 4−7. General-Purpose Bus Base Address Register
BIT FIELD NAME TYPE DESCRIPTION
31−8 AVAIL_ADD RW
Available address bits. Bits 31−8 allow the host to map the PCI2040’s 128 bytes of control space into
memory.
7−4 RSVD R Reserved. Bits 7−4 return 0s when read.
3 PREFETCHABLE R Prefetchable. This bit is hardwired to 0 in the PCI2040. The control space is not prefetchable.
2−1 TYPE R
Type. Bits 2−1 indicate the size of the base address and how it can be mapped into the host memory.
These bits are hardwired to 00 in the PCI2040 to indicate that a 32-bit base address register is used
which can be located anywhere in memory.
0 MEM_IND R
Memory space indicator. This bit indicates whether the base address maps into the host’s memory or
I/O space. This bit is hardwired to 0 in the PCI2040 to indicate that this register is memory-mapped.
4.14 Subsystem Vendor ID Register
The subsystem vendor ID register is used for system identification purposes and may be required for certain operating
systems. This register is read-only or read/write depending on the value of bit 0 (SUBSYSRW) in the miscellaneous
control register (see Section 4.26). When bit 0 (SUBSYSRW) is 0, this register is read/write and when bit 0 is 1, this
register is read-only. This register may be loaded from the serial ROM.
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name Subsystem vendor ID
Type R R R R R R R R R R R R R R R R
Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Register: Subsystem vendor ID
Type: Read-only
Offset: 2Ch
Default: 0000h