Datasheet

4−8

4.12 Control Space Base Address Register

The control space base address register allows the host to map the PCI2040’s 32K bytes of control space into host

memory.

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Name Control space base address

Type RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW

Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Name Control space base address

Type RW R R R R R R R R R R R R R R R

Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Type: Read-only, Read/Write

Offset: 14h

Default: 0000 0000h

Table 4−6. Control Space Base Address Register

BIT FIELD NAME TYPE DESCRIPTION

31−15 AVAIL_ADD RW

Available address bits. Bits 31−15 allow the host to map the PCI2040’s 32K bytes of control space into

memory. See Sections 3.5.2, DSP Chip Selects, and 3.5.3, HPI Register Access Control, for details

on addressing the control space.

14−4 RSVD R Reserved. Bits 14−4 return 0s when read.

3 PREFETCHABLE R Prefetchable. This bit is hardwired to 0 in the PCI2040. The control space is not prefetchable.

2−1 TYPE R

Type. Bits 2 and 1 indicate the size of the base address and how it can be mapped into the host memory.

These bits are hardwired to 00 in the PCI2040 to indicate that a 32-bit base address register is used

which can be located anywhere in memory.

0 MEM_IND R

Memory space indicator. This bit indicates whether the base address maps into the host’s memory or

I/O space. This bit is hardwired to 0 in the PCI2040 to indicate that the control space is

memory-mapped.