Datasheet

4−7

4.11 HPI CSR Memory Base Address Register

The HPI CSR memory base address register provides a method of allowing the host to map the PCI2040’s HPI CSR

registers into host memory space.

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Name HPI CSR memory base address

Type RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW

Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Name HPI CSR memory base address

Type RW RW RW RW R R R R R R R R R R R R

Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Type: Read-only, Read/Write

Offset: 10h

Default: 0000 0000h

Table 4−5. HPI CSR Memory Base Address Register

BIT FIELD NAME TYPE DESCRIPTION

31−12 AVAIL_ADD RW

Available address bits. These bits can be written by the host in order to allow initialization of the base

address at startup. The PCI memory address space is on the 4-Kbyte boundary.

11−4 UNAVAIL_ADD R Unavailable address bit. Bits 11−4 return 00h when read.

3 PREFETCHABLE R Prefetchable. This bit is hardwired to 0 in the PCI2040.

2−1 TYPE R

Type. Bits 2 and 1 indicate the size of the base address and how it can be mapped into the host memory.

These bits are hardwired to 00 in the PCI2040 to indicate that a 32-bit base address register is used

which can be located anywhere in memory.

0 MEM_IND R

Memory space indicator. This bit indicates whether the base address maps into the host’s memory or

I/O space. This bit is hardwired to 0 in the PCI2040 to indicate that this base address is valid only for

memory accesses.