Datasheet

4−5
4.6 Class Code
The class code register categorizes the function as a bridge device (06h), and another bridge device (80h) with a
standard programming interface (00h). Subclass and base class are loaded via serial ROM.
Bit 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name Class code
Base class Subclass Programming interface
Type R R R R R R R R R R R R R R R R R R R R R R R R
Default 0 0 0 0 0 1 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Register: Class code
Type: Read-only
Offset: 09h
Default: 068000h
4.7 Cache Line Size Register
The cache line size register is programmed by the host software to indicate the cache line size.
Bit 7 6 5 4 3 2 1 0
Name Cache line size
Type RW RW RW RW RW RW RW RW
Default 0 0 0 0 0 0 0 0
Register: Cache line size
Type: Read/Write
Offset: 0Ch
Default: 00h
4.8 Latency Timer Register
The latency timer register returns 0s when read since the PCI2040 is a target-only device.
Bit 7 6 5 4 3 2 1 0
Name Latency timer
Type R R R R R R R R
Default 0 0 0 0 0 0 0 0
Register: Latency timer
Type: Read-only
Offset: 0Dh
Default: 00h