Datasheet
4−4
4.4 PCI Status Register
The PCI status register provides the host information to the host system. A bit in this register is reset when 1 is written
to it. A 0 written to a bit has no effect.
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name PCI status
Type RC RC R R RC R R R R R R R R R R R
Default 0 0 0 0 0 0 1 0 0 0 0 1 0 0 0 0
Register: PCI status
Type: Read-only, Read/Write to Clear
Offset: 06h
Default: 0210h
Table 4−4. PCI Status Register
BIT FIELD NAME TYPE DESCRIPTION
15 PAR_ERR RC Detected parity error. This bit is set by the PCI2040 to indicate that it detected a parity error.
14 SYS_ERR RC
Signaled system error. This bit is set by the PCI2040 to indicate that it signaled a system error on the
SERR
pin. This bit can be reset by writing a 1.
13 MABORT R Receive master abort. This bit is set to indicate a transaction has been terminated due to a master abort.
12 TABT_REC R Receive target abort. This bit is set when a transaction is terminated by a target abort.
11 TABT_SIG RC
Signaled target abort. This bit is set by the PCI slave unit in the PCI2040 to indicate that it has initiated
a target abort.
10−9 PCI_SPEED R
DEVSEL timing. Bits 10 and 9 encode the timing of DEVSEL and are hardwired to 01b indicating that
the PCI2040 asserts PCI_SPEED at a medium speed on nonconfiguration cycle accesses.
8 DATAPAR R
Data parity error detected. This bit is implemented by the bus mastering devices to indicate that a parity
error has been detected.
7 FBB_CAP R
Fast back-to-back capable. This bit indicates that the device is capable of performing fast back-to-back
transactions. Since the PCI2040 does not support fast back-to-back transactions, this bit is hardwired
to 0.
6 UDF R User definable feature support. Bit 6 is hardwired to 0 indicating that the PCI2040 does not support UDF.
5 66MHZ R 66-MHz capable. Bit 5 is hardwired to 0 indicating that the PCI2040 does not support 66 MHz operations.
4 CAPLIST R
Capabilities list. Bit 4 returns 1 when read indicating that capabilities in addition to standard capabilities
are implemented.
3−0 RSVD R Reserved. Bits 3−0 return 0s when read.
4.5 Revision ID
This register indicates the silicon revision of the PCI2040.
Bit 7 6 5 4 3 2 1 0
Name Revision ID
Type R R R R R R R R
Default 0 0 0 0 0 0 0 0
Register: Revision ID
Type: Read-only
Offset: 08h
Default: 00h