Datasheet

3−7
As a side note, HINT is generated when the HINT bit is set in the HPI control register. See Section 6, DSP HPI
Overview, for a description of the DSPs HPI control register.
3.7.3 HPI Error Interrupts and HPI Error Reporting
Bit 30 (HPIError) in the interrupt event register (see Section 5.1), set upon serious error conditions on the HPI
interface, allows software to gracefully terminate communication with an HPI device. Bit 30 is set when any of the
bits in the HPI error report register (see Section 5.3) are set (an OR combination).
Bits 3−0 (HPIErr[3:0] field) in the HPI error report register (see Section 5.3) are set for an HPI interface when a cycle
destined for a particular interface experienced as serious error, which may be a result of a DSP losing power. Such
error conditions are as follows:
1. HRDY5xn (or HRDY6xn
) driven by DSP is not asserted within 256 PCI clock cycles following assertion
of HCSn
. This timer can be disabled by setting bit 1 (ErrorTimer) in the diagnostic register (see
Section 4.27).
2. The discard timeout expires for a read transaction from HPI(x)
3. A PCI byte enable combination other than 4’b1100, 4’b0011, or 4’b0000 was received for a transaction
destined for a C54x DSP on HPI(x)
To avoid potential system level catastrophe when the PCI target abort is signaled, PCI2040 implements a feature to
disable target aborts and returns zero data on such error conditions. This mode of operation is enabled via bit 30
(HPIError) in the interrupt mask register (see Section 5.2). When bit 31 is set and bit 30 (HPIError) in the interrupt
event register is also set, on all HPI error conditions, an INTA
interrupt is signaled.
Also when bit 30 (HPIError) in the interrupt mask register is set, error on posted writes will not cause the SERR
signal
assertion by bit 8 (SERR_EN) in the PCI command register (see Section 4.3). When bit 30 (HPIError) is 0, target
aborts may occur and SERR
may be signaled as a result of a posted write error. This mode of operation is not related
to SERR
signaling on PCI address parity errors per the PCI Local Bus Specification.
Future generations of PCI2040 may support connections to different numbers of DSPs (more or less than 4). A
recommended procedure for software to determine the maximum number of DSP HPI connections is to write all 1s
to the HPI error report register and read back the number of set bits. Similarly, software can perform the same
procedure on the lower 16 bits of the interrupt mask or interrupt event register.
3.7.4 General-Purpose Interrupts
The GPIO3 and GPIO2 terminals may be configured via the GPIO select register (see Section 4.21) as general
interrupt event inputs. The general interrupt event type may be either input low signal or input state change, and is
programmable via the GPIO interrupt event type register (see Section 4.25). When these general interrupt events
occur, the corresponding bits 28 (IntGPIO3) and 27 (IntGPIO2) are set in the interrupt event register (see Section 5.1)
and may be enabled to generate an interrupt (INTA
) via interrupt mask register (see Section 5.2).
3.7.5 Interrupts Versus PME
When an unmasked interrupt event occurs and PCI2040 is in the D0 power state, PCI2040 asserts INTA to signal
the interrupt event. When PCI2040 is in D1, D2, or D3, INTA
generation is disabled regardless of the value of bit 31
(masterIntEnable) in the interrupt mask register (see Section 5.2).
Whenever an unmasked interrupt event occurs and bit 15 (PME_STS) in the power management control/status
register is set (see Section 4.31), a PME
power management event is generated if bit 8 (PME_EN) in the power
management control/status register is set.
3.8 PCI2040 Power Management
This section covers the power management aspects of PCI2040, including descriptions of power savings features.