Datasheet

3−4
The HPI DSP implementation register and HPI data width register may be loaded from a serial ROM. Also, these
registers are implemented as read/write so intelligent software can load them with the proper values.
3.5.2 DSP Chip Selects
The PCI2040 provides four chip select outputs (HCS3−HCS0) that uniquely select each HPI port DSP (or other HPI
peripheral) per transaction. This section describes how software encodes the chip select in the PCI address to access
a particular DSP interfacing with PCI2040.
The PCI2040’s control space base address register (see Section 4.12) is a standard PCI base address register
requesting 32K bytes of control space nonprefetchable memory to access up to four DSPs. The PCI2040 claims PCI
memory access transactions that fall within the 32-Kbyte memory window by comparing the upper 17 bits of the PCI
address (PCI_AD31−PCI_AD15) to bits 31−15 (AVAIL_ADD field) in the control space base address register. When
a cycle is claimed, the chip select is determined by decoding bits 14 and 13 of the PCI address. PCI_AD14 and
PCI_AD13 determine the chip select according to Table 3−1.
Only when the PCI cycle is claimed (by decoding PCI_AD31−PCI_AD15) is the chip select asserted.
Table 3−1. PCI2040 Chip Select Decoding
PCI_AD(14−13) CHIP SELECT ASSERTED
2’b00 HCS0
2’b01 HCS1
2’b10 HCS2
2’b11 HCS3
3.5.3 HPI Register Access Control
The HCNTL1 and HCNTL0 terminals are driven by the PCI2040 to select the DSP HPI register and access mode
on a cycle-by-cycle basis. The PCI2040 determines the type of DSP register access from the PCI address, similarly
to the chip select decode as described in Section 3.5.2, DSP Chip Selects.
When a cycle is claimed by decoding PCI_AD31−PCI_AD15, the HCNTL1 and HCNTL0 control signals are
determined by decoding bits 12 and 11 of PCI address. PCI_AD12 maps to HCNTL1 and PCI_AD11 maps to
HCNTL0, and the selected HCNTL1 and HCNTL0 are driven to the HPI interface when the cycle is forwarded.
Table 6−1 and Table 6−3 provides more information on the usage of HCNTL1 and HCNTL0 for both C54x and C6x
DSPs.
3.5.4 Mapping HPI DSP Memory to the Host
The PCI address bits PCI_AD10−PCI_AD0 are not forwarded to the HPI interface, and these address bits are not
decoded by PCI2040 for any purpose. This 2-Kbyte of addressable space per DSP (and control) allows the host to
directly map 2K bytes of host memory to the HPI interface for each DSP. This allows for fast memory block copies
rather than an I/O port mechanism.
The PCI2040 does not automatically generate accesses to the HPI address registers based upon
PCI_AD10−PCI_AD0, and it is left to software to synchronize the HPI address register with copies to and from HPI
memory space.
3.5.5 Read/Write Procedure
The following procedure illustrates how to read and write HPI space, and covers some of the initialization that must
be done to successfully transfer data to and from DSP memory via the HPI data register.
After a power-on reset (GRST
):
• PCI2040 preloads several registers if a serial ROM is implemented, and this rewrites the HPI
implementation and HPI data width registers (software can also rewrite these registers).