Datasheet

3−2

3.2 Accessing Internal PCI2040 Registers

PCI configuration space is accessed via PCI configuration read and PCI configuration write cycles. These registers

may be accessed using byte, word, or double-word transfers.

The PCI2040 provides a set of registers specifically for interfacing with the HPI port. These registers are called the

HPI control and status registers (HPI CSRs) (see Section 5), and they may be memory- and I/O-mapped. The HPI

CSR memory base address register (see Section 4.11) provides the mechanism for mapping the HPI CSRs into

memory space. When mapped into memory space, the HPI CSRs may be accessed using bytes, words, or

double-word transfers. Memory mapping the HPI CSR registers is recommended.

The HPI control and status registers may also be mapped into I/O space via the HPI CSR I/O base address register

(see Section 4.32). When this register is programmed to a nonzero value, PCI2040 maps the HPI CSRs into I/O

space, and the index/data access scheme is used to access the registers using byte transfers.

The HPI CSR I/O base address register identifies the I/O address of the index port. I/O address index + 1 is the data

port. To access a HPI CSR register, software writes the offset of the HPI CSR register into the index port. I/O reads

from the data port provide the contents of the indexed register and writes to the data port result in PCI2040 updating

the indexed register.

3.3 PCI_LOCK

PCI2040 supports exclusive access via the LOCK protocol defined by PCI and the PCI_LOCK terminal. As a PCI

target, PCI2040 locks all DSP access and internal resources to a particular master when PCI_LOCK

is sampled

deasserted during the address phase of a PCI cycle that it claims. Once LOCK

is established, the PCI2040 remains

locked until both FRAME

and LOCK are sampled deasserted or bit 30 (HPIError) is set in the interrupt event register

(see Section 5.1).

The master that owns the exclusive access lock on PCI2040 drives PCI_LOCK

while the lock is established and

deasserts PCI_LOCK

(and asserts FRAME) when addressing the PCI2040. The PCI2040 claims and retries cycles

addressed to it when PCI_LOCK

is asserted. Other masters will not be able to force the PCI_LOCK signal high when

addressing a locked PCI2040 and will be retried.

Note that when the PCI2040 is not locked, it can claim and complete data transfers even if PCI_LOCK

is sampled

asserted in the address phase.

3.4 Serial ROM Interface

The PCI2040 provides a two-wire serial ROM interface that may be used to preload PCI2040 registers following a

power-on reset (GRST

). The serial ROM interface includes a serial clock (SCL) output and a serial data (SDA)

input/output. The SCL signal maps to the GPIO0 terminal and the SDA signal maps to the GPIO1 terminal. The

two-wire serial ROM interface is enabled by pulling up both GPIO0 and GPIO1 terminals to V

with resistors. The

PCI2040 will only sense GPIO0 on GRST

to identify the serial ROM; thus, only GPIO0 must be tied low to disable

the serial ROM interface.

The registers that may be preloaded are given in the following list, and only write accessible bits in these registers