Datasheet

4−27

4.38 Power-Management Control/Status Register

The power-management control/status register determines and changes the current power state of the PCI1520

CardBus function. The contents of this register are not affected by the internally-generated reset caused by the

transition from D3

hot

to D0 state. All PCI, ExCA, and CardBus registers are reset as a result of a D3

hot

to D0 state

transition. TI-specific registers, PCI power-management registers, and the PC Card 16-bit legacy-mode base

address register (PCI offset 44h, see Section 4.28) are not reset. See Table 4−15 for a complete description of the

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Name Power-management control/status

Type RC R R R R R R RW R R R R R R RW RW

Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Offset: A4h (functions 0, 1)

Type: Read-only, Read/Write, Read/Clear

Default: 0000h

Table 4−15. Power-Management Control/Status Register Description

BIT SIGNAL TYPE FUNCTION

15 PMESTAT RC

PME status. Bit 15 is set when the CardBus function would normally assert PME, independent

of the state of bit 8 (PME_EN). Bit 15 is cleared by a writeback of 1, and this also clears the PME

signal if PME was asserted by this function. Writing a 0 to this bit has no effect.

14−13 DATASCALE R

Data scale. This 2-bit field returns 0s when read. The CardBus function does not return any

dynamic data.

12−9 DATASEL R

Data select. This 4-bit field returns 0s when read. The CardBus function does not return any

dynamic data.

8 PME_EN RW

PME enable. Bit 8 enables the function to assert PME. If this bit is cleared, then assertion of PME

is disabled.

7−2 RSVD R Reserved. Bits 7−2 return 0s when read.

1−0 PWR_STATE RW

Power state. This 2-bit field is used both to determine the current power state of a function and

to set the function into a new power state. This field is encoded as:

00 = D0

01 = D1

10 = D2

11 = D3

hot