Datasheet

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4.33 Device Control Register

The device control register is provided for PCI1130 compatibility and contains bits that are shared between functions

0 and 1. The interrupt mode select is programmed through this register which is composed of PCI1520 global bits.

The socket-capable force bits are also programmed through this register. See Table 4−12 for a complete description

of the register contents.

Bit 7 6 5 4 3 2 1 0

Name Device control

Type RW RW RW R RW RW RW RW

Default 0 1 1 0 0 1 1 0

Offset: 92h (functions 0, 1)

Type: Read-only, Read/Write

Default: 66h

Table 4−12. Device Control Register Description

BIT SIGNAL TYPE FUNCTION

7 SKTPWR_LOCK RW

Socket power lock bit. When this bit is set to 1, software cannot power down the PC Card socket while

in D3. This may be necessary to support wake on LAN or RING if the operating system is programmed

to power down a socket when the CardBus controller is placed in the D3 state.

†

3VCAPABLE RW

3-V socket capable force

0 = Not 3-V capable

1 = 3-V capable (default)

5 IO16V2 RW Diagnostic bit. This bit defaults to 1.

4 RSVD R Reserved. Bit 4 returns 0 when read.

†

TEST RW TI test. Only a 0 should be written to bit 3.

2−1 INTMODE RW

Interrupt signaling mode. Bits 2 and 1 select the interrupt signaling mode. The interrupt signaling

mode bits are encoded:

00 = Parallel PCI interrupts only

01 = Parallel IRQ and parallel PCI interrupts

10 = IRQ serialized interrupts and parallel PCI interrupt

11 = IRQ and PCI serialized interrupts (default)

†

RSVD RW Reserved. Bit 0 is reserved for test purposes. Only 0 should be written to this bit.

†

This bit is global and is accessed only through function 0.