Datasheet

4−11

4.20 Memory Limit Registers 0, 1

The memory limit registers indicate the upper address of a PCI memory address range. These registers are used

by the PCI1520 to determine when to forward a memory transaction to the CardBus bus and when to forward a

CardBus cycle to PCI. Bits 31−12 of these registers are read/write and allow the memory base to be located anywhere

in the 32-bit PCI memory space on 4-Kbyte boundaries. Bits 11−0 are read-only and always return 0s. Write

transactions to these bits have no effect. Bits 8 and 9 of the bridge control register specify whether memory windows

0 and 1 are prefetchable or nonprefetchable. The memory base register or the memory limit register must be nonzero

for the PCI1520 to claim any memory transactions through CardBus memory windows; that is, these windows are

not enabled by default to pass the first 4 Kbytes of memory to CardBus.

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Name Memory limit registers 0, 1

Type RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW

Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Name Memory limit registers 0, 1

Type RW RW RW RW R R R R R R R R R R R R

Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Offset: 20h, 28h

Type: Read-only, Read/Write

Default: 0000 0000h

4.21 I/O Base Registers 0, 1

The I/O base registers indicate the lower address of a PCI I/O address range. These registers are used by the

PCI1520 to determine when to forward an I/O transaction to the CardBus bus and when to forward a CardBus cycle

to the PCI bus. The lower 16 bits of this register locate the bottom of the I/O window within a 64-Kbyte page, and the

upper 16 bits (31−16) are a page register which locates this 64-Kbyte page in 32-bit PCI I/O address space. Bits 31−2

are read/write. Bits 1 and 0 are read-only and always return 0s, forcing I/O windows to be aligned on a natural

doubleword boundary.

NOTE: Either the I/O base register or the I/O limit register must be nonzero to enable any I/O

transactions.

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Name I/O base registers 0, 1

Type RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW

Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Name I/O base registers 0, 1

Type RW RW RW RW RW RW RW RW RW RW RW RW RW RW R R

Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Offset: 2Ch, 34h

Type: Read-only, Read/Write

Default: 0000 0000h