Datasheet

4−5
4.6 Revision ID Register
The revision ID register indicates the silicon revision of the PCI1520.
Bit 7 6 5 4 3 2 1 0
Name Revision ID
Type R R R R R R R R
Default 0 0 0 0 0 0 0 1
Register: Revision ID
Offset: 08h (functions 0, 1)
Type: Read-only
Default: 01h
4.7 PCI Class Code Register
The class code register recognizes PCI1520 functions 0 and 1 as a bridge device (06h) and a CardBus bridge device
(07h), with a 00h programming interface.
Bit 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name PCI class code
Base class Subclass Programming interface
Type R R R R R R R R R R R R R R R R R R R R R R R R
Default 0 0 0 0 0 1 1 0 0 0 0 0 0 1 1 1 0 0 0 0 0 0 0 0
Register: PCI class code
Offset: 09h (functions 0, 1)
Type: Read-only
Default: 06 0700h
4.8 Cache Line Size Register
The cache line size register is programmed by host software to indicate the system cache line size.
Bit 7 6 5 4 3 2 1 0
Name Cache line size
Type RW RW RW RW RW RW RW RW
Default 0 0 0 0 0 0 0 0
Register: Cache line size
Offset: 0Ch (functions 0, 1)
Type: Read/Write
Default: 00h