Datasheet

4−4
4.5 Status Register
The status register provides device information to the host system. Bits in this register can be read normally. A bit
in the status register is reset when a 1 is written to that bit location; a 0 written to a bit location has no effect. All bit
functions adhere to the definitions in the PCI Local Bus Specification. PCI bus status is shown through each function.
See Table 4−4 for a complete description of the register contents.
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name Status
Type RC RC RC RC RC R R RC R R R R R R R R
Default 0 0 0 0 0 0 1 0 0 0 0 1 0 0 0 0
Register: Status
Offset: 06h (functions 0, 1)
Type: Read-only, Read/Clear
Default: 0210h
Table 4−4. Status Register Description
BIT SIGNAL TYPE FUNCTION
15 PAR_ERR RC Detected parity error. Bit 15 is set when a parity error is detected (either address or data).
14 SYS_ERR RC Signaled system error. Bit 14 is set when SERR is enabled and the PCI1520 signals a system error to the host.
13 MABORT RC
Received master abort. Bit 13 is set when a cycle initiated by the PCI1520 on the PCI bus is terminated by a
master abort.
12 TABT_REC RC
Received target abort. Bit 12 is set when a cycle initiated by the PCI1520 on the PCI bus is terminated by a target
abort.
11 TABT_SIG RC
Signaled target abort. Bit 11 is set by the PCI1520 when it terminates a transaction on the PCI bus with a target
abort.
10−9 PCI_SPEED R
DEVSEL timing. These bits encode the timing of DEVSEL and are hardwired 01b, indicating that the PCI1520
asserts PCI_SPEED at a medium speed on nonconfiguration cycle accesses.
8 DATAPAR RC
Data parity error detected.
0 = The conditions for setting bit 8 have not been met.
1 = A data parity error occurred, and the following conditions were met:
a. PERR
was asserted by any PCI device including the PCI1520.
b. The PCI1520 was the bus master during the data parity error.
c. The parity error response bit is set in the command register (PCI offset 04h, see Section 4.4).
7 FBB_CAP R
Fast back-to-back capable. The PCI1520 cannot accept fast back-to-back transactions; therefore, bit 7 is
hardwired to 0.
6 UDF R
User-definable feature support. The PCI1520 does not support the user-definable features; therefore, bit 6 is
hardwired to 0.
5 66MHZ R
66-MHz capable. The PCI1520 operates at a maximum PCLK frequency of 33 MHz; therefore, bit 5 is hardwired
to 0.
4 CAPLIST R
Capabilities list. Bit 4 returns 1 when read. This bit indicates that capabilities in addition to standard PCI
capabilities are implemented. The linked list of PCI power-management capabilities is implemented in this
function.
3−0 RSVD R Reserved. Bits 3−0 return 0s when read.