Datasheet

2−20
Table 2−14. CardBus PC Card Address and Data Terminals (Slots A and B)
TERMINAL
NUMBER
I/O
DESCRIPTION
NAME
SLOT A
†
SLOT B
‡
I/O
DESCRIPTION
NAME
PDV GHK PDV GHK
CAD31
CAD30
CAD29
CAD28
CAD27
CAD26
CAD25
CAD24
CAD23
CAD22
CAD21
CAD20
CAD19
CAD18
CAD17
CAD16
CAD15
CAD14
CAD13
CAD12
CAD11
CAD10
CAD9
CAD8
CAD7
CAD6
CAD5
CAD4
CAD3
CAD2
CAD1
CAD0
151
149
148
146
145
136
135
134
131
129
127
125
123
122
121
104
102
103
101
100
99
98
97
94
93
89
90
87
88
85
86
84
E19
G15
F18
G14
G17
J14
J17
J18
K15
K18
L14
L17
L19
M19
M18
W16
R14
U15
V15
P14
W15
U14
R13
P13
U13
P12
R12
V12
U12
R11
W12
P11
82
79
78
77
76
67
66
65
63
60
59
57
55
54
53
36
34
35
33
32
31
30
28
26
25
21
22
19
20
17
18
16
V11
R10
U10
V10
W10
R08
W07
V07
P08
V06
U06
V05
R06
U05
W04
M03
M01
M02
L05
L06
L03
L02
K06
K03
K02
J03
J05
J01
J02
H02
H01
H03
I/O
CardBus address and data. These signals make up the multiplexed CardBus address
and data bus on the CardBus interface. During the address phase of a CardBus cycle,
CAD31−CAD0 contain a 32-bit address. During the data phase of a CardBus cycle,
CAD31−CAD0 contain data. CAD31 is the most significant bit.
CC/BE3
CC/BE2
CC/BE1
CC/BE0
132
120
105
96
K14
M17
T19
V14
64
52
37
27
U07
T01
M06
K05
I/O
CardBus bus commands and byte enables. CC/BE3−CC/BE0 are multiplexed on the
same CardBus terminals. During the address phase of a CardBus cycle,
CC/BE3−CC/BE0 define the bus command. During the data phase, this 4-bit bus is used
as byte enables. The byte enables determine which byte paths of the full 32-bit data bus
carry meaningful data. CC/BE0
applies to byte 0 (CAD7−CAD0), CC/BE1 applies to
byte 1 (CAD15−CAD8), CC/BE2
applies to byte 2 (CAD23−CAD16), and CC/BE3
applies to byte 3 (CAD31−CAD24).
CPAR 107 P15 40 N02 I/O
CardBus parity. In all CardBus read and write cycles, the PCI1520 calculates even parity
across the CAD and CC/BE
buses. As an initiator during CardBus cycles, the PCI1520
outputs CPAR with a one-CCLK delay. As a target during CardBus cycles, the PCI1520
compares its calculated parity to the parity indicator of the initiator; a compare error
results in a parity error assertion.
†
Terminal name for slot A is preceded with A_. For example, the full name for terminals 107 and P15 is A_CPAR.
‡
Terminal name for slot B is preceded with B_. For example, the full name for terminals 40 and N02 is B_CPAR.