Datasheet

2−11
The terminals are grouped in tables by functionality, such as PCI system function, power-supply function, etc. The
terminal numbers are also listed for convenient reference.
Table 2−5. Power Supply Terminals
TERMINAL
NAME
NO.
I/O DESCRIPTION
NAME
PDV GHK
I/O
DESCRIPTION
GND
6, 24, 43, 62,
95, 110, 147,
166, 185, 199
A06, A09, A14,
E01, F19, K01,
P01, R19, W06,
W14
−
Device ground terminals
V
CC
14, 39, 70, 91,
118, 133, 143,
174, 195
A07, A12, G01,
G19, J19, N01,
N19, W08, W13
−
Power supply terminal for I/O and internal voltage regulator
V
CCA
114 P19 −
Clamp voltage for PC Card A interface. Matches card A signaling environment, 5 V
or 3.3 V
V
CCB
47 R01 −
Clamp voltage for PC Card B interface. Matches card B signaling environment, 5 V
or 3.3 V
V
CCP
180 A10 − Clamp voltage for PCI and miscellaneous I/O, 5 V or 3.3 V
VR_EN 29 L01 I Internal voltage regulator enable. Active-low
VR_PORT 128 K19 I/O
Internal voltage regulator input/output. When VR_EN is low, the regulator is en-
abled and this terminal is an output. An external bypass capacitor is required on this
terminal. When VR_EN is high, the regulator is disabled and this terminal is an input
for an external 2.5-V core power source.
Table 2−6. PC Card Power Switch Terminals
TERMINAL
NAME
NO.
I/O DESCRIPTION
NAME
PDV GHK
I/O
DESCRIPTION
CLOCK 154 F15 I/O
Power switch clock. Information on the DATA line is sampled at the rising edge of CLOCK. CLOCK defaults to
an input, but can be changed to a PCI1520 output by using bit 27 (P2CCLK) in the system control register
(offset 80h, see Section 4.29). The TPS222X defines the maximum frequency of this signal to be 2 MHz. How-
ever, PCI1520 requires a 16-KHz to 100-KHz frequency range. If a system design defines this terminal as an
output, then this terminal requires an external pulldown resistor. The frequency of the PCI1520 output CLOCK
is derived from the internal ring oscillator (16 KHz typical).
DATA 155 E17 O
Power switch data. DATA is used to communicate socket power control information serially to the power
switch.
LATCH 153 E18 I/O
Power switch latch. LATCH is asserted by the PCI1520 to indicate to the power switch that the data on the
DATA line is valid. When a pulldown resistor is implemented on this terminal, the MFUNC1 and MFUNC4 ter-
minals provide the serial EEPROM SDA and SCL interface.