Datasheet

6−9
6.6 Socket Power-Management Register
This register provides power management control over the socket through a mechanism for slowing or stopping the
clock on the card interface when the card is idle. See Table 6−7 for a complete description of the register contents.
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name Socket power-management
Type R R R R R R R R R R R R R R R RW
Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name Socket power-management
Type R R R R R R R R R R R R R R R RW
Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Register: Socket power-management
Type: Read-only, Read/Write
Offset: CardBus socket address + 20h
Default: 0000 0000h
Table 6−7. Socket Power-Management Register Description
BIT SIGNAL TYPE FUNCTION
31−26 RSVD R Reserved. Bits 31−26 return 0s when read.
25 SKTACCES R
Socket access status. This bit provides information on when a socket access has occurred. This bit is
cleared by a read access.
0 = A PC card access has not occurred (default).
1 = A PC card access has occurred.
24 SKTMODE R
Socket mode status. This bit provides clock mode information.
0 = Clock is operating normally.
1 = Clock frequency has changed.
23−17 RSVD R Reserved. Bits 23−17 return 0s when read.
16 CLKCTRLEN RW
CardBus clock control enable. When bit 16 is set, bit 0 (CLKCTRL) is enabled.
0 = Clock control is disabled (default).
1 = Clock control is enabled.
15−1 RSVD R Reserved. Bits 15−1 return 0s when read.
0 CLKCTRL RW
CardBus clock control. This bit determines whether the CB CLKRUN protocol stops or slows the CB clock
during idle states. Bit 16 (CLKCTRLEN) enables this bit.
0 = Allows CB CLKRUN protocol to stop the CB clock (default).
1 = Allows CB CLKRUN
protocol to slow the CB clock by a factor of 16.