Datasheet

6−3
6.2 Socket Mask Register
The socket mask register allows software to control the CardBus card events that generate a status change interrupt.
The state of these mask bits does not prevent the corresponding bits from reacting in the socket event register (CB
offset 00h, see Section 6.1). See Table 6−3 for a complete description of the register contents.
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name Socket mask
Type R R R R R R R R R R R R R R R R
Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name Socket mask
Type R R R R R R R R R R R R RW RW RW RW
Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Register: Socket mask
Offset: CardBus socket address + 04h
Type: Read-only, Read/Write
Default: 0000 0000h
Table 6−3. Socket Mask Register Description
BIT SIGNAL TYPE FUNCTION
31−4 RSVD R Reserved. Bits 31−4 return 0s when read.
3 PWRMASK RW
Power cycle. Bit 3 masks bit 3 (PWRCYCLE) in the socket present-state register (CB offset 08h, see
Section 6.3) from causing a status change interrupt.
0 = PWRCYCLE event does not cause CSC interrupt (default).
1 = PWRCYCLE event causes CSC interrupt.
2−1 CDMASK RW
Card detect mask. Bits 2 and 1 mask bits 1 and 2 (CDETECT1 and CDETECT2) in the socket present-state
register (CB offset 08h, see Section 6.3) from causing a CSC interrupt.
00 = Insertion/removal does not cause CSC interrupt (default).
01 = Reserved (undefined)
10 = Reserved (undefined)
11 = Insertion/removal causes CSC interrupt.
0 CSTSMASK RW
CSTSCHG mask. Bit 0 masks bit 0 (CARDSTS) in the socket present-state register (CB offset 08h, see
Section 6.3) from causing a CSC interrupt.
0 = CARDSTS event does not cause CSC interrupt (default).
1 = CARDSTS event causes CSC interrupt.