Datasheet

6−2
6.1 Socket Event Register
The socket event register indicates a change in socket status has occurred. These bits do not indicate what the
change is, only that one has occurred. Software must read the socket present-state register (CB offset 08h, see
Section 6.3) for current status. Each bit in this register can be cleared by writing a 1 to that bit. The bits in this register
can be set to a 1 by software by writing a 1 to the corresponding bit in the socket force event register (CB offset 0Ch,
see Section 6.4). All bits in this register are cleared by PCI reset. They can be immediately set again, if, when coming
out of PC Card reset, the bridge finds the status unchanged (that is, CSTSCHG
reasserted or card detect is still true).
Software must clear this register before enabling interrupts. If it is not cleared when interrupts are enabled, then an
interrupt is generated (but not masked) based on any bit set. See Table 6−2 for a complete description of the register
contents.
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name Socket event
Type R R R R R R R R R R R R R R R R
Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name Socket event
Type R R R R R R R R R R R R R/C R/C R/C R/C
Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Register: Socket event
Offset: CardBus socket address + 00h
Type: Read-only, Read/Write, Read/Clear
Default: 0000 0000h
Table 6−2. Socket Event Register Description
BIT SIGNAL TYPE FUNCTION
31−4 RSVD R Reserved. Bits 31−4 return 0s when read.
3 PWREVENT R/C
Power cycle. Bit 3 is set when the PCI1520 detects that bit 3 (PWRCYCLE) in the socket present-state
register (CB offset 08h, see Section 6.3) has changed state. This bit is cleared by writing a 1.
2 CD2EVENT R/C
CCD2. Bit 2 is set when the PCI1520 detects that bit 2 (CDETECT2) in the socket present-state register
(CB offset 08h, see Section 6.3) has changed state. This bit is cleared by writing a 1.
1 CD1EVENT R/C
CCD1. Bit 1 is set when the PCI1520 detects that bit 1 (CDETECT1) in the socket present-state register
(CB offset 08h, see Section 6.3) has changed state. This bit is cleared by writing a 1.
0 CSTSEVENT R/C
CSTSCHG. Bit 0 is set when bit 0 (CARDSTS) in the socket present-state register (CB offset 08h, see
Section 6.3) has changed state. For CardBus cards, bit 0 is set on the rising edge of CSTSCHG
. For 16-bit
PC Cards, bit 0 is set on both transitions of CSTSCHG
. This bit is reset by writing a 1.