Datasheet

6−1
6 CardBus Socket Registers (Functions 0 and 1)
The 1997 PC Card Standard requires a CardBus socket controller to provide five 32-bit registers that report and
control socket-specific functions. The PCI1520 provides the CardBus socket/ExCA base-address register (PCI offset
10h, see Section 4.12) to locate these CardBus socket registers in PCI memory address space. Each socket has a
separate base address register for accessing the CardBus socket registers (see Figure 6−1). Table 6−1 gives the
location of the socket registers in relation to the CardBus socket/ExCA base address.
The PCI1520 implements an additional register at offset 20h that provides power management control for the socket.
CardBus Socket/ExCA Base Address
16-Bit Legacy-Mode Base Address
10h
44h
NOTE: The CardBus socket/ExCA base address mode register is separate for functions 0 and 1.
PCI1520 Configuration Registers
CardBus
Socket A
Registers
Host
Memory Space
00h
ExCA
Registers
Card A
20h
800h
844h
Offset
CardBus
Socket B
Registers
Host
Memory Space
00h
ExCA
Registers
Card B
20h
800h
844h
Offse
t
Offset
Figure 6−1. Accessing CardBus Socket Registers Through PCI Memory
Table 6−1. CardBus Socket Registers
REGISTER NAME OFFSET
Socket event 00h
Socket mask 04h
Socket present-state 08h
Socket force event 0Ch
Socket control 10h
Reserved 14h−1Ch
Socket power-management 20h
A bit description table, typically included when a register contains bits of more than one type or purpose, indicates
bit field names, which appear in the signal column; a detailed field description, which appears in the function column;
and field access tags, which appear in the type column of the bit description table. Table 4−2 describes the field
access tags.