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4.42 General-Purpose Event Enable Register
The general-purpose event enable register contains bits that are set to enable a GPE signal. The GPE signal is driven
until the corresponding status bit is cleared and the event is serviced. The GPE
can only be signaled if one of the
multifunction terminals, MFUNC6−MFUNC0, is configured for GPE
signaling. See Table 4−17 for a complete
description of the register contents.
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Register: General-purpose event enable
Offset: AAh
Type: Read-only, Read/Write
Default: 0000h
Table 4−17. General-Purpose Event Enable Register Description
BIT SIGNAL TYPE FUNCTION
15 ZV0_EN RW
PC Card ZV enable. When bit 15 is set, a GPE is signaled on a change in status of bit 6 (ZVENABLE) in
the card control register (PCI offset 91h, see Section 4.32).
14−12 RSVD R Reserved. Bits 14−12 return 000b when read.
11 PWR_EN RW
Power change enable. When bit 11 is set, a GPE is signaled on when software has changed the power
state.
10−9 RSVD R Reserved. Bits 10 and 9 return 00b when read.
8 VPP12_EN RW
12-V V
PP
request enable. When bit 8 is set, a GPE is signaled when software has changed the requested
V
PP
level to or from 12 V.
7−5 RSVD R Reserved. Bits 7−5 return 000b when read.
4 GP4_EN RW
GPI4 enable. When bit 4 is set, a GPE is signaled when there has been a change in status of the MFUNC5
terminal input level if configured as GPI4.
3 GP3_EN RW
GPI3 enable. When bit 3 is set, a GPE is signaled when there has been a change in status of the MFUNC4
terminal input level if configured as GPI3.
2 GP2_EN RW
GPI2 enable. When bit 2 is set, a GPE is signaled when there has been a change in status of the MFUNC2
terminal input if configured as GPI2.
1 GP1_EN RW
GPI1 enable. When bit 1 is set, a GPE is signaled when there has been a change in status of the MFUNC1
terminal input if configured as GPI1.
0 GP0_EN RW
GPI0 enable. When bit 0 is set, a GPE is signaled when there has been a change in status of the MFUNC0
terminal input if configured as GPI0.