Datasheet

4−17
Table 4−8. Multifunction Routing Register Description (Continued)
BIT SIGNAL TYPE FUNCTION
7−4 MFUNC1 RW
Multifunction terminal 1 configuration. These bits control the internal signal mapped to the MFUNC1 terminal
as follows:
NOTE: When the serial bus mode is implemented by pulling up the VCCD0
and VCCD1 terminals, the
MFUNC1 terminal provides the SDA signaling.
0000 = GPI1
†
0100 = IRQ4 1000 = CAUDPWM 1100 = LED_SKT
0001 = GPO1 0101 = IRQ5 1001 = IRQ9 1101 = IRQ13
0010 = D3_STAT
0110 = ZVSTAT 1010 = IRQ10 1110 = GPE
0011 = IRQ3 0111 = ZVSEL0 1011 = IRQ11 1111 = IRQ15
3−0 MFUNC0 RW
Multifunction terminal 0 configuration. These bits control the internal signal mapped to the MFUNC0 terminal
as follows:
0000 = GPI0
†
0100 = IRQ4 1000 = CAUDPWM 1100 = LED_SKT
0001 = GPO0 0101 = IRQ5 1001 = IRQ9 1101 = IRQ13
0010 = INTA
0110 = ZVSTAT 1010 = IRQ10 1110 = GPE
0011 = IRQ3 0111 = ZVSEL0 1011 = IRQ11 1111 = IRQ15
†
Default value
4.31 Retry Status Register
The retry status register enables the retry timeout counters and displays the retry expiration status. The flags are set
when the controller retries a PCI or CardBus master request and the master does not return within 2
15
PCI clock
cycles. The flags are cleared by writing a 1b to the bit. These bits are expected to be incorporated into the PCI
command, PCI status, and bridge control registers by the PCI SIG. See Table 4−9 for a complete description of the
register contents.
Bit 7 6 5 4 3 2 1 0
Default 1 1 0 0 0 0 0 0
Register: Retry status
Offset: 90h
Type: Read-only, Read/Write, Read/Clear
Default: C0h
Table 4−9. Retry Status Register Description
BIT SIGNAL TYPE FUNCTION
7 PCIRETRY RW
PCI retry timeout counter enable. Bit 7 is encoded:
0 = PCI retry counter disabled
1 = PCI retry counter enabled (default)
6 CBRETRY RW
CardBus retry timeout counter enable. Bit 6 is encoded:
0 = CardBus retry counter disabled
1 = CardBus retry counter enabled (default)
5 TEXP_CBB RC
CardBus target B retry expired. Write a 1b to clear bit 5.
0 = Inactive (default)
1 = Retry has expired
4 RSVD R Reserved. Bit 4 returns 0b when read.
3 TEXP_CBA RC
CardBus target A retry expired. Write a 1b to clear bit 3.
0 = Inactive (default)
1 = Retry has expired
2 RSVD R Reserved. Bit 2 returns 0b when read.
1 TEXP_PCI RC
PCI target retry expired. Write a 1b to clear bit 1.
0 = Inactive (default)
1 = Retry has expired
0 RSVD R Reserved. Bit 0 returns 0b when read.