Datasheet

4−14
4.29 System Control Register
System-level initializations are performed by programming this doubleword register. See Table 4−7 for a complete
description of the register contents.
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Default 0 0 0 0 1 0 0 0 0 1 0 0 0 1 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Default 1 0 0 1 0 0 0 0 0 1 1 0 0 0 0 0
Register: System control
Offset: 80h
Type: Read-only, Read/Write, Read/Clear
Default: 0844 9060h
Table 4−7. System Control Register Description
BIT SIGNAL TYPE FUNCTION
31−30 SER_STEP RW
Serialized PCI interrupt routing step. Bits 31 and 30 configure the serialized PCI interrupt stream signaling
and accomplish an even distribution of interrupts signaled on the four PCI interrupt slots.
00 = INTA
signal in INTA IRQSER slots
01 = INTA
signal in INTB IRQSER slots
10 = INTA
signal in INTC IRQSER slots
11 = INTA
signal in INTD IRQSER slots
29−28 RSVD R Reserved. Bit 28 returns 0b when read.
27 OSEN R/W
Internal oscillator enable.
0 = Internal oscillator is disabled
1 = Internal oscillator is enabled (default)
26 SMIROUTE RW
SMI interrupt routing. Bit 26 selects whether IRQ2 or CSC is signaled when a write occurs to power a PC Card
socket.
0 = PC Card power change interrupts routed to IRQ2 (default)
1 = A CSC interrupt is generated on PC Card power changes
25 SMISTATUS RC
SMI interrupt status. This bit is set when bit 24 (SMIENB) is set and a write occurs to set the socket power.
Writing a 1b to bit 25 clears the status.
0 = SMI interrupt signaled (default)
1 = SMI interrupt not signaled
24 SMIENB RW
SMI interrupt mode enable. When bit 24 is set and a write to the socket power control occurs, the SMI interrupt
signaling is enabled and generates an interrupt. This bit defaults to 0b (disabled).
23 RSVD R Reserved. Bit 23 returns 0b when read.
22 CBRSVD RW
CardBus reserved terminals signaling. When a CardBus card is inserted and bit 22 is set, the RSVD CardBus
terminals are driven low. When this bit is 0b, these terminals are placed in a high-impedance state.
0 = Place CardBus RSVD terminals in a high-impedance state
1 = Drive Cardbus RSVD terminals low (default)
21 VCCPROT RW
V
CC
protection enable.
0 = V
CC
protection enabled for 16-bit cards (default)
1 = V
CC
protection disabled for 16-bit cards
20 REDUCEZV RW
Reduced zoomed video enable. When this bit is enabled, terminals A25−A22 of the card interface for PC
Card-16 cards are placed in the high-impedance state. This bit should not be set for normal ZV operation. This
bit is encoded as:
0 = Reduced zoomed video disabled (default)
1 = Reduced zoomed video enabled
19−16 RSVD RW Reserved. Do not change the default value.