Datasheet

4−8
4.15 PCI Bus Number Register
This register is programmed by the host system to indicate the bus number of the PCI bus to which the controller is
connected. The controller uses this register in conjunction with the CardBus bus number and subordinate bus number
registers to determine when to forward PCI configuration cycles to its secondary buses.
Bit 7 6 5 4 3 2 1 0
Default 0 0 0 0 0 0 0 0
Register: PCI bus number
Offset: 18h
Type: Read/Write
Default: 00h
4.16 CardBus Bus Number Register
This register is programmed by the host system to indicate the bus number of the CardBus bus to which the controller
is connected. The controller uses this register in conjunction with the PCI bus number and subordinate bus number
registers to determine when to forward PCI configuration cycles to its secondary buses.
Bit 7 6 5 4 3 2 1 0
Default 0 0 0 0 0 0 0 0
Register: CardBus bus number
Offset: 19h
Type: Read/Write
Default: 00h
4.17 Subordinate Bus Number Register
This register is programmed by the host system to indicate the highest-numbered bus below the CardBus bus. The
controller uses this register in conjunction with the PCI bus number and CardBus bus number registers to determine
when to forward PCI configuration cycles to its secondary buses.
Bit 7 6 5 4 3 2 1 0
Default 0 0 0 0 0 0 0 0
Register: Subordinate bus number
Offset: 1Ah
Type: Read/Write
Default: 00h
4.18 CardBus Latency Timer Register
This register is programmed by the host system to specify the latency timer for the CardBus interface in units of CCLK
cycles. When the controller is a CardBus initiator and asserts CFRAME
, the CardBus latency timer begins counting.
If the latency timer expires before the transaction has terminated, then the controller terminates the transaction at
the end of the next data phase. A recommended minimum value for this register is 40h, which allows most
transactions to be completed.
Bit 7 6 5 4 3 2 1 0
Default 0 0 0 0 0 0 0 0
Register: CardBus latency timer
Offset: 1Bh
Type: Read/Write
Default: 00h