Datasheet

4−5
4.7 PCI Class Code Register
The class code register recognizes the controller as a bridge device (06h) and a CardBus bridge device (07h), with
a 00h programming interface.
Bit 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name Base class Subclass Programming interface
Default 0 0 0 0 0 1 1 0 0 0 0 0 0 1 1 1 0 0 0 0 0 0 0 0
Register: PCI class code
Offset: 09h
Type: Read-only
Default: 06 0700h
4.8 Cache Line Size Register
The cache line size register is programmed by host software to indicate the system cache line size.
Bit 7 6 5 4 3 2 1 0
Default 0 0 0 0 0 0 0 0
Register: Cache line size
Offset: 0Ch
Type: Read/Write
Default: 00h
4.9 Latency Timer Register
The latency timer register specifies the latency time for the controller in units of PCI clock cycles. When the controller
is a PCI bus initiator and asserts FRAME
, the latency timer begins counting from zero. If the latency timer expires
before the transaction has terminated, then the controller terminates the transaction when its GNT
is deasserted.
Bit 7 6 5 4 3 2 1 0
Default 0 0 0 0 0 0 0 0
Register: Latency timer
Offset: 0Dh
Type: Read/Write
Default: 00h
4.10 Header Type Register
This register returns 02h when read, indicating that the configuration space adheres to the CardBus bridge PCI
header. The CardBus bridge PCI header ranges from PCI register 00h to 7Fh, and 80h to FFh is user-definable
extension registers.
Bit 7 6 5 4 3 2 1 0
Default 0 0 0 0 0 0 1 0
Register: Header type
Offset: 0Eh
Type: Read-only
Default: 02h