Datasheet

3−12
S1 10 0 0 0 0 0 b7b6b5b4b3b2b1b0AA
Slave Address Word Address
R/W
Data Byte 2 Data Byte 1 Data Byte 0 M PMM
M = Master Acknowledgement
S/P = Start/Stop ConditionA = Slave Acknowledgement
Data Byte 3 M
S1 10 00001A
Restart
R/W
Slave Address
Start
Figure 3−13. EEPROM Interface Doubleword Data Collection
3.6.3 Serial-Bus EEPROM Application
When the PCI bus is reset and the serial-bus interface is detected, the controller attempts to read the subsystem
identification and other register defaults from a serial EEPROM. The registers and corresponding bits that can be
loaded with defaults through the EEPROM are provided in Table 3−5.
Table 3−5. Register- and Bit-Loading Map
EEPROM OFFSET REGISTER OFFSET REGISTER BITS LOADED FROM EEPROM
00h Flag 01h: Load / FFh: do not load
01h PCI 04h Command register, bit 8, 6−5, 2−0
Note: bits loaded per following:
bit 8 ← bit 7
bit 6 ← bit 6
bit 5 ← bit 5
bit 2 ← bit 2
bit 1 ← bit 1
bit 0 ← bit 0
02h PCI 40h Subsystem vendor ID bits 7−0 ← bits 7−0
03h PCI 40h Subsystem vendor ID bits 15−8 ← bits 7−0
04h PCI 42h Subsystem ID bits 7−0 ← bits 7−0
05h PCI 42h Subsystem ID bits 15−8 ← bits 7−0
06h PCI 44h PC Card 16-bit I/F LBAR bits 7−1 ← bits 7−1
07h PCI 44h PC Card 16-bit I/F LBAR bits 15−8 ← bits 7−0
08h PCI 44h PC Card 16-bit I/F LBAR bits 23−16 ← bits 7−0
09h PCI 44h PC Card 16-bit I/F LBAR bits 31−24 ← bits 7−0
0Ah PCI 80h System control bits 7−0 ← bits 7−0
0Bh PCI 80h System control bits 15−8 ← bits 7−0
0Ch PCI 80h System control bits 23−16 ← bits 7−0
0Dh PCI 80h System control bits 31−24 ← bits 7−0
0Eh PCI 8Ch Multifunction routing bits 7−0 ← bits 7−0
0Fh PCI 8Ch Multifunction routing bits 15−8 ← bits 7−0
10h PCI 8Ch Multifunction routing bits 23−16 ← bits 7−0
11h PCI 8Ch Multifunction routing bits 27−24 ← bits 3−0
12h PCI 90h Retry status bits 7, 6 ← bits 7, 6
13h PCI 91h Card control bit 7 ← bit 7
14h PCI 92h Device control bits 6, 3−0 ← bits 6, 3−0
15h PCI 93h Diagnostic bits 7, 4–0 ← bits 7, 4−0
16h PCI A2h Power management capabilities bit 15 ← bit 7
17h ExCA 00h ExCA identification and revision bits 7–0 ← bits 7−0
18h CB Socket + 0Ch Socket force event, bit 27 ← bit 3