Datasheet

3−11
SCL From
Master
123 789
SDA Output
By Transmitter
SDA Output
By Receiver
Figure 3−10. Serial-Bus Protocol Acknowledge
The controller is a serial bus master; all other devices connected to the serial bus external to the controller are slave
devices. As the bus master, the controller drives the SCL clock at nearly 100 kHz during bus cycles and places SCL
in a high-impedance state (zero frequency) during idle states.
Typically, the controller masters byte reads and byte writes under software control. Doubleword reads are performed
by the serial EEPROM initialization circuitry upon a PCI reset and may not be generated under software control. See
Section 3.6.3, Serial-Bus EEPROM Application, for details on how the controller automatically loads the subsystem
identification and other register defaults through a serial-bus EEPROM.
Figure 3−11 illustrates a byte write. The controller issues a start condition and sends the 7-bit slave device address
and the command bit zero. A 0b in the R/W
command bit indicates that the data transfer is a write. The slave device
acknowledges if it recognizes the address. If no acknowledgment is received by the controller, then an appropriate
status bit is set in the serial-bus control and status register (PCI offset B3h, see Section 4.48). The word address byte
is then sent by the controller, and another slave acknowledgment is expected. Then the controller delivers the data
byte MSB first and expects a final acknowledgment before issuing the stop condition.
Sb6 b4b5 b3 b2 b1 b0 0 b7 b6 b5 b4 b3 b2 b1 b0AA
Slave Address Word Address
R/W
S/P = Start/Stop ConditionA = Slave Acknowledgement
b7 b6 b4b5 b3 b2 b1 b0 A P
Data Byte
Figure 3−11. Serial-Bus Protocol − Byte Write
Figure 3−12 illustrates a byte read. The read protocol is very similar to the write protocol, except the R/W
command
bit must be set to 1b to indicate a read-data transfer. In addition, the master must acknowledge reception of the read
bytes from the slave transmitter. The slave transmitter drives the SDA signal during read data transfers. The SCL
signal remains driven by the master.
Sb6 b4b5 b3 b2 b1 b0 0 b7 b6 b5 b4 b3 b2 b1 b0AA
Slave Address Word Address
R/W
Sb6 b4b5 b3 b2 b1 b0 1 A
Slave Address
S/P = Start/Stop ConditionM = Master Acknowledgement
b7 b6 b4b5 b3 b2 b1 b0 M P
Data Byte
Start
Restart R/W
A = Slave Acknowledgement
Stop
Figure 3−12. Serial-Bus Protocol − Byte Read
Figure 3−13 illustrates EEPROM interface doubleword data collection protocol.