Datasheet

2−23
Table 2−15. CardBus PC Card Address and Data Terminals
TERMINAL
NAME
NUMBER
I/O DESCRIPTION
NAME
PGE GGU GVF
I/O
DESCRIPTION
CAD31
CAD30
CAD29
CAD28
CAD27
CAD26
CAD25
CAD24
CAD23
CAD22
CAD21
CAD20
CAD19
CAD18
CAD17
CAD16
CAD15
CAD14
CAD13
CAD12
CAD11
CAD10
CAD9
CAD8
CAD7
CAD6
CAD5
CAD4
CAD3
CAD2
CAD1
CAD0
144
142
141
140
139
129
128
127
123
121
120
118
116
115
114
97
95
96
94
92
91
90
89
87
86
82
83
79
81
77
78
76
B03
B04
C04
C05
A04
C07
D07
B07
D10
B12
C08
C09
B09
A12
B10
F10
C11
F11
F12
G12
G10
G13
G11
H11
H12
K13
J10
J11
J13
M12
K12
K11
E08
C08
B08
E09
F09
F11
E11
C11
A12
C12
E12
C13
A14
E13
B14
F18
G17
F19
G18
H15
H14
H17
H18
J14
J17
K14
J19
K17
K15
L14
K18
L15
I/O
CardBus address and data. These signals make up the multiplexed CardBus address and data
bus on the CardBus interface. During the address phase of a CardBus cycle, CAD31–CAD0
contain a 32-bit address. During the data phase of a CardBus cycle, CAD31–CAD0 contain
data. CAD31 is the most significant bit.
CC/BE3
CC/BE2
CC/BE1
CC/BE0
124
113
98
88
A08
D09
E11
H13
B11
C14
G15
J15
I/O
CardBus bus commands and byte enables. CC/BE3–CC/BE0 are multiplexed on the same
CardBus terminals. During the address phase of a CardBus cycle, CC/BE3
–CC/BE0 define the
bus command. During the data phase, this 4-bit bus is used as a byte enable. The byte enable
determines which byte paths of the full 32-bit data bus carry meaningful data. CC/BE0 applies
to byte 0 (CAD7–CAD0), CC/BE1
applies to byte 1 (CAD15–CAD8), CC/BE2 applies to byte 2
(CAD23–CAD16), and CC/BE3
applies to byte (CAD31–CAD24).
CPAR 100 E12 F14 I/O
CardBus parity. In all CardBus read and write cycles, the controller calculates even parity
across the CAD and CC/BE
buses. As an initiator during CardBus cycles, the controller outputs
CPAR with a one-CCLK delay. As a target during CardBus cycles, the controller compares its
calculated parity to the parity indicator of the initiator; a compare error results in a parity error
assertion.