Datasheet

2−22
Table 2−13. 16-Bit PC Card Interface Control Terminals (Continued)
TERMINAL
NAME
NUMBER
I/O DESCRIPTION
NAME
PGE GGU GVF
I/O
DESCRIPTION
VS1
VS2
130
117
B02
A09
B10
F12
I/O
Voltage sense 1 and voltage sense 2. VS1 and VS2, when used in conjunction with each other,
determine the operating voltage of the PC Card.
WAIT 133 B06 E10
I
Bus cycle wait. WAIT is driven by a 16-bit PC Card to extend the completion of the memory or
I/O in progress.
WE 105 D13 D19 O
Write enable. WE is used to strobe memory write data into 16-bit memory PC Cards. WE is also
used for memory PC Cards that employ programmable memory technologies.
WP
(IOIS16
)
136 A05 B09 I
Write protect. WP applies to 16-bit memory PC Cards. WP reflects the status of the write-protect
switch on 16-bit memory PC Cards. For 16-bit I/O cards, WP is used for the 16-bit port (IOIS16
)
function.
I/O is 16 bits. IOIS16 applies to 16-bit I/O PC Cards. IOIS16 is asserted by the 16-bit PC Card
when the address on the bus corresponds to an address to which the 16-bit PC Card responds,
and the I/O port that is addressed is capable of 16-bit accesses.
Table 2−14. CardBus PC Card Interface System Terminals
TERMINAL
NAME
NUMBER
I/O DESCRIPTION
NAME
PGE GGU GVF
I/O
DESCRIPTION
CCLK 107 B13 C15 O
CardBus clock. CCLK provides synchronous timing for all transactions on the CardBus
interface. All signals except CRST
, CCLKRUN, CINT, CSTSCHG, CAUDIO, CCD2, CCD1,
CVS2, and CVS1 are sampled on the rising edge of CCLK, and all timing parameters are
defined with the rising edge of this signal. CCLK operates at the PCI bus clock frequency, but
it can be stopped in the low state or slowed down for power savings.
CCLKRUN 136 A05 B09 I/O
CardBus clock run. CCLKRUN is used by a CardBus PC Card to request an increase in the
CCLK frequency, and by the controller to indicate that the CCLK frequency is going to be
decreased.
CRST 119 D08 B13 O
CardBus reset. CRST brings CardBus PC Card-specific registers, sequencers, and signals
to a known state. When CRST
is asserted, all CardBus PC Card signals are placed in a
high-impedance state, and the controller drives these signals to a valid logic level. Assertion
can be asynchronous to CCLK, but deassertion must be synchronous to CCLK.