Datasheet

2−17
Table 2−9. PCI Address and Data Terminals
TERMINAL
NAME
NUMBER
I/O DESCRIPTION
NAME
PGE GGU GVF
I/O
DESCRIPTION
AD31
AD30
AD29
AD28
AD27
AD26
AD25
AD24
AD23
AD22
AD21
AD20
AD19
AD18
AD17
AD16
AD15
AD14
AD13
AD12
AD11
AD10
AD9
AD8
AD7
AD6
AD5
AD4
AD3
AD2
AD1
AD0
3
4
5
6
7
9
10
11
15
16
17
18
22
23
24
25
38
39
41
42
43
44
45
46
48
49
50
51
52
53
55
56
E03
D03
E04
D02
B01
F04
E02
F03
C03
F01
G04
G02
H02
H03
H01
J04
M04
L05
K05
N03
L04
M05
M02
N04
N05
L06
M06
K04
N06
L07
M07
N08
J05
J06
K02
K03
K05
K06
L02
L03
M02
M03
M06
M05
N02
N03
N06
P01
R06
P07
V05
U06
V06
R04
P08
U07
W07
R08
U08
V08
W09
V09
U09
R09
I/O
PCI address/data bus. These signals make up the multiplexed PCI address and data bus on the
primary interface. During the address phase of a primary-bus PCI cycle, AD31–AD0 contain a
32-bit address or other destination information. During the data phase, AD31–AD0 contain data.
C/BE3
C/BE2
C/BE1
C/BE0
13
26
37
47
A01
J02
M03
K06
L06
P02
U05
V07
I/O
PCI-bus commands and byte enables. These signals are multiplexed on the same PCI
terminals. During the address phase of a primary-bus PCI cycle, C/BE3
–C/BE0 define the bus
command. During the data phase, this 4-bit bus is used as a byte enable. The byte enable
determines which byte paths of the full 32-bit data bus carry meaningful data. C/BE0 applies to
byte 0 (AD7–AD0), C/BE1
applies to byte 1 (AD15–AD8), C/BE2 applies to byte 2
(AD23–AD16), and C/BE3
applies to byte 3 (AD31–AD24).
PAR 35 N01 W04 I/O
PCI-bus parity. In all PCI-bus read and write cycles, the controller calculates even parity across
the AD31–AD0 and C/BE3
–C/BE0 buses. As an initiator during PCI cycles, the controller outputs
this parity indicator with a one-PCLK delay. As a target during PCI cycles, the controller
compares its calculated parity to the parity indicator of the initiator. A compare error results in the
assertion of a parity error (PERR
).