Datasheet

2−16
Table 2−8. PCI System Terminals
TERMINAL
NAME
NUMBER
I/O DESCRIPTION
NAME
PGE GGU GVF
I/O
DESCRIPTION
GRST 66 L11 H02 I
Global reset. When the global reset is asserted, the GRST signal causes the controller to
place all output buffers in a high-impedance state and reset all internal registers. When GRST
is asserted, the device is completely in its default state. For systems that require wake-up
from D3, GRST
normally is asserted only during initial boot. PRST must be asserted following
initial boot so that PME context is retained during the transition from D3 to D0.
When the SUSPEND
mode is enabled, the device is protected from GRST, and the internal
registers are preserved. All outputs are placed in a high-impedance state.
PCLK 20 G01 H01 I
PCI bus clock. PCLK provides timing for all transactions on the PCI bus. All PCI signals are
sampled at the rising edge of PCLK.
PRST 19 G03 H03 I
PCI bus reset. When the PCI bus reset is asserted, PRST causes the controller to place all
output buffers in a high-impedance state and reset internal registers. When PRST
is asserted,
the device can generate the PME
signal only if it is enabled. After PRST is deasserted, the
controller is in a default state.
When the SUSPEND
mode is enabled, the device is protected from PRST, and the internal
registers are preserved. All outputs are placed in a high-impedance state.